UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 379

• Manufacturer Part Number: UPD70F3737GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

cleared from FFFFH to 0000H, starts incrementing, and outputs a PWM waveform from the TOQ0k pin. If the trigger
is generated again while the counter is incrementing, the counter is cleared to 0000H and restarts incrementing, and
the output of the TOQ00 pin is inverted. (The TOQ0k pin outputs a high level signal regardless of the status (high/low)
when a trigger occurs.)
time after its value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
INTTQ0CCk compare match interrupt request signal is generated when the value of the 16-bit counter matches the
value of the CCRk buffer register.
is used as the trigger.
TQ0CTL0
When the TQ0CE bit is set to 1, TMQ0 waits for a trigger. When the trigger is generated, the 16-bit counter is
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The INTTQ0CC0 compare match interrupt request signal is generated when the 16-bit counter increments next
Either the valid edge of the external trigger input signal or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1
Remark
Active level width = (Set value of TQ0CCRk register) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)
(a) TMQ0 control register 0 (TQ0CTL0)
k = 1 to 3
TQ0CE
0/1
Figure 8-28. Register Settings in External Trigger Pulse Output Mode (1/3)
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
0
User’s Manual U18953EJ5V0UD
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
0/1
0/1
0/1
These bits select
the count clock.
0: Stop counting.
1: Enable counting.
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