UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 428
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UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(c) Processing an overflow when two or more capture registers are used
Figure 8-60. Example of Incorrect Processing When Two or More Capture Registers Are Used
Care must be exercised in processing the overflow flag when two or more capture registers are used. First,
an example of incorrect processing is shown below.
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> The TQ0CCR0 register is read (the default value of the TIQ00 pin input is set).
<2> The TQ0CCR1 register is read (the default value of the TIQ01 pin input is set).
<3> The TQ0CCR0 register is read.
<4> The TQ0CCR1 register is read.
When two or more capture registers are used, and if the TQ0OVF bit is cleared to 0 by one capture
register, another capture register may not obtain the correct pulse width.
This problem can be resolved by using software, as shown in the example below.
TQ0CCR0 register
TQ0CCR1 register
INTTQ0OV signal
The TQ0OVF bit is read. If the TQ0OVF bit is 1, it is cleared to 0.
Because the TQ0OVF bit is 1, the pulse width can be calculated by (10000H + D
The TQ0OVF bit is read. Because the TQ0OVF bit was cleared in <3>, 0 is read.
Because the TQ0OVF bit is 0, the pulse width can be calculated by (D
TIQ00 pin input
TIQ01 pin input
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
00
User’s Manual U18953EJ5V0UD
<1>
D
10
<2>
D
00
D
D
01
10
<3>
D
11
<4>
11
D
− D
01
10
) (incorrect).
D
11
01
− D
00
).
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