UPD70F3737GF-GAS-AX Renesas Electronics America, UPD70F3737GF-GAS-AX Datasheet - Page 404
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UPD70F3737GF-GAS-AX
Manufacturer Part Number
UPD70F3737GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3737GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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outputs a PWM waveform from the TOQ0k pin.
newly written value is reflected when the value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H.
The INTTQ0CCk compare match interrupt request signal is generated when the value of the 16-bit counter matches
the value of the CCRk buffer register.
402
TQ0CTL0
TQ0CTL1
When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts incrementing, and
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows:
The PWM waveform can be changed by rewriting the TQ0CCRm register while the counter is incrementing. The
The INTTQ0CC0 compare match interrupt request signal is generated when the 16-bit counter increments next
Remark
Active level width = (Set value of TQ0CCRk register) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
Note The setting of these bits is invalid when the TQ0CTL1.TQ0EEE bit is 1.
k = 1 to 3
m = 0 to 3
TQ0CE
0/1
0
TQ0EST
0
0
Figure 8-46. Register Settings in PWM Output Mode (1/3)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0EEE
0/1
0
0
0
User’s Manual U18953EJ5V0UD
0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
TQ0MD2 TQ0MD1 TQ0MD0
0/1
1
0/1
0
0/1
0
1, 0, 0:
PWM output mode
0: Operate on count clock
1: Increment based on external
These bits select the
count clock
0: Stop counting.
1: Enable counting.
selected by using TQ0CKS0
to TQ0CKS2 bits.
event count input signal.
Note
.
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