AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 146

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 21-6.
21.6.5.3
146
Mode
Attribute Memory
Common Memory
I/O Mode
True IDE Mode
Alternate True IDE Mode
True IDE Standby
Mode or Address
Space is not assigned
to CF
Alternate Status Read
Control Register
Drive Address
AT91SAM9261S
Data Register
Read/Write Signals
CFCE1 and CFCE2 Truth Table
Task File
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the Static Memory Controller section.
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command
signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deac-
tivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are
driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated.
21-4 on page 147
Attribute memory mode, common memory mode and I/O mode are supported by setting the
address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values.
CFCE2
NBS1
NBS1
NBS1
1
1
1
1
0
0
1
CFCE1
demonstrates a schematic representation of this logic.
NBS0
NBS0
NBS0
0
0
0
0
1
1
1
16 bits
16 bits
16 bits
16bits
DBW
8 bits
8 bits
8 bits
Don’t
8 bits
Don’t
Care
Care
Comment
Access to Even Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Don’t Care
SMC Access Mode
Byte Select
Byte Select
Don’t Care
Byte Select
Don’t Care
Don’t Care
Byte Select
Don’t Care
Don’t Care
Don’t Care
6242E–ATARM–11-Sep09
Figure