AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 694

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

694
Doc. Rev.
6242C
AT91SAM9261S
Date
12-Sep-08 Comments (Continued)
LCDC: (continued)
”Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is
configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2) LCDDOTCK
cycles.” on page
HFP+2 (not HFP+1) idem for
Section 38.10.12 ”LCD Timing Configuration Register 2”
and the timing diagrams
Figure 38-3 ”STN Panel Timing, CLKMOD 0”
Figure 38-4 ”TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1”
Figure 38-5 ”TFT Panel Timing (Line Expanded View), CLKMOD=1”
PMC:
Section 26.1 ”Overview”
Section 26.3 ”Processor Clock
Figure 25-1 ”Typical Slow Clock Crystal Oscillator
Section 26.7 ”Programming
to 0...”
RSTC:
Figure 14-4 ”Genera Reset
Section 14.3.4.1 ”General
Section 14.3.3 ”BMS Sampling”
Section 14.3.4.4 ”Software
purposes.
SHDWC:
Table 18-2, “Register Mapping”
SHDW_MR reset changed to 0x0000_0303.
SHDW_SR offset value is 0x08.
SDRAMC:
Section 23.6.1 ”SDRAMC Mode
Section 23.6.3 ”SDRAMC Configuration Register”
SMC:
Section 22.8.5 ”Coding Timing
updated in
Section 22.9.3.1 ”User
Chip Select added
SPI:
Section 30.6.4 ”SPI Slave
SPI_RDR.
Section 30.7.9 ”SPI Chip Select
referenced in the BITS bit field description and
SSC:
Section 33.8.3 ”SSC Receive Clock Mode
16.
Table
598.
22-4.
Procedure”, added instructions regarding configuration parameters of SMC
• PCK must be switched off when entering processor in Idle Mode.
Reset”, extensive update to this section.
Mode”, corrected information on OVRES (SPI_SR) and data read in
Reset”, PERRST must be used with PROCRST, except for debug
State”, updated
Sequence”, correction to
Controller”, updated with information on “Wait for Interrupt Mode”.
Parameters”, “Effective Value” column under “Permitted Range”
and
Register”, note pertaining to BITS field added. This note is
Register”, changed MODE bit descriptions.
Figure 14-3 ”BMS Sampling”
Register”, Corrected name to STTDLY in bit fields 23 to
Section 30.6.4 ”SPI Slave
Changed bit description for
Connection”, GNDPLL changed to GNDBU.
Step
5, and
Step
added to datasheet
6, “....PRES parameter is set
Mode”.
“CAS: CAS
Latency”.
6242E–ATARM–11-Sep09
Change
Request
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