AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 657

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

39.9
6242E–ATARM–11-Sep09
SDRAMC TImings
The timings that follow are given for a 10 pF load on SDCK and 50 pF on the databus.
Table 39-21. SDRAMC Clock Signal
Table 39-22. SDRAM Signals
Symbol
1/(t
Symbol
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
SDRAMC
CPSDCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
)
Parameter
SDRAM Controller Clock Frequency
Parameter
SDCKE High before SDCK Rising Edge
SDCKE Low after SDCK Rising Edge
SDCKE Low before SDCK Rising Edge
SDCKE High after SDCK Rising Edge
SDCS Low before SDCK Rising Edge
SDCS High after SDCK Rising Edge
RAS Low before SDCK Rising Edge
RAS High after SDCK Rising Edge
SDA10 Change before SDCK Rising Edge
SDA10 Change after SDCK Rising Edge
Address Change before SDCK Rising Edge
Address Change after SDCK Rising Edge
Bank Change before SDCK Rising Edge
Bank Change after SDCK Rising Edge
See
MCK Maximum Clock Frequency
1.8V Supply
Waveform Parameters”
Table 39-6, “Master Clock
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
Supply
1.8V
AT91SAM9261S
0.8
0.3
0.4
0.2
1.5
0.3
0.4
0.4
0.4
0.3
3.6
0.4
3.3
0.5
Max
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
3.3V Supply
Min
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
CPSDCK
Supply
3.3V
0.8
0.4
0.2
0.2
1.2
0.3
0.2
0.4
0.5
0.4
3.7
0.5
3.3
0.5
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
/2 -
Units
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
657