AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 566
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AT91SAM9261SB-CU-999
Manufacturer Part Number
AT91SAM9261SB-CU-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261SB-CU-999.pdf
(709 pages)
Specifications of AT91SAM9261SB-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, I2S, SPI, USB
Maximum Clock Frequency
190 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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37.5.3.6
37.5.3.7
37.5.3.8
566
AT91SAM9261S
Entering in Suspend State
Receiving a Host Resume
Sending a Device Remote Wakeup
When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the
UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR
register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend
Mode.
In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an exam-
ple, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes
into Idle Mode. It may also switch off other devices on the board.
The USB device peripheral clocks can be switched off. Resume event is asynchronously
detected. MCK and UDPCK can be switched off in the Power Management controller and the
USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the
UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations
after writing to the UDP_TXVC and acknowledging the RXSUSP.
In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver
and clocks are disabled (however the pullup shall not be removed).
Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may gen-
erate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be
used to wake up the core, enable PLL and main oscillators and configure clocks.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the
UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the
UDP_ICR register and clearing TXVDIS in the UDP_TXVC register.
In Suspend state it is possible to wake up the host sending an external resume.
To force a K state to the bus (DM at 3.3V and DP tied to GND), it is possible to use a transistor
to connect a pullup on DM. The K state is obtained by disabling the pullup on DP and enabling
the pullup on DM. This should be under the control of the application.
• The device must wait at least 5 ms after being entered in suspend before sending an external
• The device has 10 ms from the moment it starts to drain current and it forces a K state to
• The device must force a K state from 1 to 15 ms to resume the host
resume.
resume the host.
6242E–ATARM–11-Sep09
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