AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 184

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Figure 22-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
Figure 22-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
184
read1 controlling signal
read2 controlling signal
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS0, NBS1,
NBS2, NBS3,
A0, A1
AT91SAM9261S
A
[25:2]
D[31:0]
A[
D[31:0]
(NRD)
(NRD)
(NWE)
(NRD)
selects
MCK
25:2]
MCK
TDF_CYCLES = 6
TDF_CYCLES = 4
read1 cycle
read1 cycle
read1 hold = 1
read1 hold = 1
Chip Select Wait State
TDF_CYCLES = 4
Read to Write
Wait State
TDF_CYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
write2 cycle
(optimization disabled)
6242E–ATARM–11-Sep09
TDF_MODE = 0
read2 setup = 1
read 2 cycle