AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 46

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.3
46
CP15 Coprocessor
AT91SAM9261S
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the
items in the list below:
To control these features, CP15 provides 16 additional registers. See
Table 11-5.
Notes:
• ARM9EJ-S
• Caches (ICache, DCache and write buffer)
• MMU
• Other system options
Register
1. Register locations 0, 5 and 13 each provide access to more than one register. The register
2. Register location 9 provides access to more than one register. The register accessed depends
10
11
12
13
13
14
15
0
0
1
2
3
4
5
5
6
7
8
9
accessed depends on the value of the opcode_2 field.
on the value of the CRm field.
CP15 Registers
Name
ID Code
Cache type
Control
Translation Table Base
Domain Access Control
Reserved
Data fault Status
Instruction fault status
Fault Address
Cache Operations
TLB operations
Cache lockdown
TLB lockdown
Reserved
Reserved
FCSE PID
Context ID
Reserved
Test configuration
(1)
(1)
(1)
(1)
(2)
(1)
(1)
Read/Unpredictable
Read/Unpredictable
Read/write
Read/write
Read/write
None
Read/write
Read/write
Read/write
Read/Write
Read/write
Read/write
None
None
Read/write
Read/Write
None
Read/Write
Read/Write
Unpredictable/Write
Table
11-5.
6242E–ATARM–11-Sep09