MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 68

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Parallel I/O Ports (PORTS)
7.3.3 Pulldown Register B
Pulldown register B inhibits the pulldown devices on port B pins programmed as inputs.
PDIB[3:2] — Pulldown Inhibit B Bits
68
PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Note:
Address:
1. Writing affects the data register, but does not affect input.
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port B pins as inputs with disabled pulldown devices.
Reset:
These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are con-
Read:
Write:
figured as inputs.
Data Direction Bit
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
$0011
Bit 7
0
1
= Unimplemented
Figure 7-9. Pulldown Register B (PDRB)
6
Table 7-2. Port B Pin Operation
Input, high-impedance
5
0
See Note
I/O Pin Mode
Output
NOTE
4
0
PDIB3
3
0
Read
Latch
PDIB2
Accesses to Data Bit
Pin
2
0
1
0
See Note
Latch
Write
Latch
Freescale Semiconductor
(1)
Bit 0
0