HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 202

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM
data must be held after a reset, take one of the measures described below.
1. When resetting manually, use the watchdog timer (WDT) reset function.
2. Even if the low width of RAS becomes as short as 1.5 tcyc as shown above, use with a
3.
These measures are not required when DRAM data is initialized or loaded again after a manual
reset.
Rev. 7.00 Jan 31, 2006 page 174 of 658
REJ09B0272-0700
A0–A21
A0–A21
frequency that satisfies the DRAM standard (t
Even if the low width of RAS is 1.5 tcyc, use an external circuit so that a RAS signal with a
low width of 2.5 tcyc is input in the DRAM (if the low width of RAS is higher than 2.5 tcyc,
operate so that the current waveform is input in the DRAM).
RES
RAS
CAS
RES
RAS
CAS
RD
RD
CK
CK
RES latch
timing
RES latch
Figure 8.40 Long-Pitch Mode Read (1)
Figure 8.41 Long-Pitch Mode Read (2)
Manual reset
timing
Manual reset
Tp
Tp
RAS
Row address
Row address
).
Tr
Tr
Column address
FFFF
Tc1
Tc1
FFFF
Tc2
Tc2