HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 599

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table A.5
Bit Bit Name
7
6
5
4
3
2
1
0
Transmit interrupt
enable (TIE)
Receive interrupt
enable (RIE)
Transmit enable (TE) 0
Receive enable (RE)
Multiprocessor inter-
rupt enable (MPIE)
Transmit end inter-
rupt enable (TEIE)
Clock enable 1
(CKE1)
Clock enable 0
(CKE0)
SCR Bit Functions
0
Value Description
0
1
0
1
1
0
1
0
1
1
0
0
1
1
0
1
0
1
Transmit data-empty interrupt request (TXI) disabled
Transmit data-empty interrupt request (TXI) enabled
Receive-data-full interrupt request (RXI) and receive-error
interrupt request (ERI) disabled
Receive-data-full interrupt request (RXI) and receive-error
interrupt request (ERI)
Transmission disabled
Transmission enabled
Reception disabled
Reception enabled
Multiprocessor interrupts disabled (normal receive operation)
Clear conditions: (1) MPIE bit cleared to zero; (2) When data
the MPB = 1 is received
Multiprocessor interrupts enabled. Disables receive interrupts
(RXI), receive error interrupts (ERI), and setting of RDRF,
FER, and ORER flags in SSR until data with a “1”
multiprocessor bit is received
Transmit interrupt requests (TEI) disabled
Transmit interrupt requests (TEI) enabled
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Asynchronous
mode
Synchronous
mode
Appendix A On-Chip Supporting Module Registers
Internal clock/SCK pin is input pin (input
signal ignored) or output pin (output level
undetermined)
Internal clock/SCK pin is synchronous
clock output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is serial clock
output
External clock/SCK pin is clock input
External clock/SCK pin is serial clock
input
External clock/SCK pin is clock input
External clock/SCK pin is serial clock
input
Rev. 7.00 Jan 31, 2006 page 571 of 658
REJ09B0272-0700
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)