HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 278

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Notes: 1. Undefined
Bits 7–3—Reserved: Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
Bit 2—Overflow Flag (OVF): OVF indicates that a TCNT overflow/underflow has occurred.
Bit 2: OVF
0
1
Note: A TCNT underflow occurs when the TCNT up/down-counter is functioning. It may occur in
Bit 1—Input Capture/Compare Match B (IMFB): IMFB indicates a GRB compare match or
input capture.
Bit 1: IMFB
0
1
Rev. 7.00 Jan 31, 2006 page 250 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
the following cases: (1) When channel 2 is set to phase counting mode (MDF bit in TMDR is
1), or (2) when channel 3 and 4 are set to complementary PWM mode (CMD1 bit in TFCR
is 1 and CMD0 bit is 0).
2. Only 0 can be written, to clear the flag.
Description
Clearing condition: Read OVF when OVF = 1, then write 0 in OVF (Initial value)
Setting condition: TCNT overflow from H'FFFF to H'0000 or underflow from
H'0000 to H'FFFF
Description
Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB
Setting conditions:
GRB is functioning as an output compare register and TCNT = GRB
GRB is functioning as an input capture register and the value of TCNT is
transferred to GRB by an input capture signal
—
—
*
7
1
—
—
6
1
—
—
5
1
—
—
4
1
—
—
3
1
R/(W) *
OVF
2
0
2
R/(W) *
IMFB
1
0
(Initial value)
2
R/(W) *
IMFA
0
0
2