HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 219

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2—Address Error Flag Bit (AE): AE indicates that an address error has occurred in the
DMAC. When this flag is set to 1, the channel cannot be enabled even if the DE bit in the DMA
channel control register (CHCR) and the DME bit are set to 1. To clear the AE bit, read 1 from it
and then write 0. It is initialized to 0 by a reset and in standby mode.
Bit 2: AE
0
1
Bit 1—NMI Flag Bit (NMIF): NMIF indicates that an NMI interrupt has occurred. When this
flag is set to 1, the channel cannot be enabled even if the DE bit in CHCR and the DME bit are set
to 1. To clear the NMIF bit, read 1 from it and then write 0. It is initialized to 0 by a reset and in
standby mode.
Bit 1: NMIF
0
1
Bit 0—DMA Master Enable Bit (DME): DME enables or disables DMA transfers on all
channels. A channel becomes enabled for a DMA transfer when the DE bit in each DMA's CHCR
and the DME bit are set to 1. For this to be effective, however, the TE bit of each CHCR and the
NMIF and AE bits must all be 0. When the DME bit is cleared, all channel DMA transfers are
aborted.
Bit 0: DME
0
1
Description
No DMAC address error
To clear the AE bit, read 1 from it and then write 0
Address error by DMAC
Description
No NMI interrupt
To clear the NMIF bit, read 1 from it and then write 0
NMI has occurred
Description
DMA transfers disabled on all channels
DMA transfers enabled on all channels
Section 9 Direct Memory Access Controller (DMAC)
Rev. 7.00 Jan 31, 2006 page 191 of 658
REJ09B0272-0700
(Initial value)
(Initial value)
(Initial value)