HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 493

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

19.1
In the power-down state, all CPU functions are halted. This lowers power consumption of the SH
microprocessor dramatically.
19.1.1
The power-down state includes the following two modes:
1. Sleep mode
2. Standby mode
Sleep mode and standby mode are entered from the program execution state according to the
transition conditions given in table 19.1. Table 19.1 also describes procedures for exiting each
mode and the states of the CPU and supporting functions.
Table 19.1 Power-Down State
SBYCR: Standby control register
SBY: Standby bit
Notes: 1. Some of the registers of the on-chip supporting modules are not initialized in standby
Mode
Sleep
mode
Standby
mode
Entering
Procedure
Execute SLEEP
instruction with
SBY bit set to 0 in
SBYCR
Execute SLEEP
instruction with
SBY bit set to 1 in
SBYCR
2. The status of I/O ports in standby mode are set by the port high-impedance bit (HIZ) in
Overview
Power-Down Modes
mode. For details, see table 19.3, Register States in Standby Mode, in section 19.4.1,
Transition to Standby Mode, or the descriptions of registers given where the on-chip
supporting modules are covered.
SBYCR. See section 19.2, Standby Control Register (SBYCR), for details. The status of
pins other than the I/O ports are described in appendix B, Pin States.
Section 19 Power-Down State
Clock
Runs
Halted Halted Halted*
CPU
Halted Run
Supporting
Functions
1
State
CPU
Registers RAM
Held
Held
Rev. 7.00 Jan 31, 2006 page 465 of 658
Held
Held
Section 19 Power-Down State
I/O
Ports
Held
Held or
high-Z*
2
Exiting Procedure
REJ09B0272-0700
Interrupt
DMA address error
Power-on reset
Manual reset
NMI interrupt
Power-on reset
Manual reset