M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 113

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
3. Interrupt discrimination bit
Use an LDM instruction to clear to “0” an interrupt discrimination
bit.
LDM #%0000XXXX, $0B
Set the following values to “X”
“0”: an interrupt discrimination bit to clear
“1”: other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is cleared;
LDM #%00001110 and $0B.
4. Interrupt discrimination bit and interrupt request bit
For key-on wakeup, UART1 bus collision detection, A/D conver-
sion and Timer 1 interrupt, even if each interrupt valid bit (interrupt
source set register (address 0A
rupt discrimination bit (interrupt source discrimination register
(address 0B
interrupt request occurs.
But corresponding interrupt request bit (interrupt request registers
1, 2 (addresses 3C
Rev.3.03
REJ03B0006-0303
16
Jul 11, 2008
)) is set to “1: interrupt occurs” when corresponding
16
, 3D
16
) is not affected.
16
Page 111 of 117
)) is set “0: Invalid”, each inter-
Notes on Timers
1. When n (0 to 255) is written to a timer latch, the frequency divi-
2. When a count source of timer X, timer A or timer B is switched,
Notes on Timer X
1. CNTR
CNTR
switch bit (bit 2 of timer X mode register (address 2B
When this bit is “0”, the CNTR
the falling edge of CNTR
CNTR
CNTR
2. Timer X count source selection
The f(X
count source selection bits (bits 1 and 0 of timer count source set
register (address 2A
on-chip oscillator is selected.
Do not select it for the timer X count source at the RC oscillation.
3. Pulse output mode
Set the direction register of port P1
pin, to output.
When the TX
which is also used as TX
4. Pulse width measurement mode
Set the direction register of port P1
pin, to input.
Notes on Timer A, B
1. Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped or operating. Accordingly, in order to set the initial value
for timer when it is stopped, set “0: Write to latch and timer simul-
taneously” to timer A (B) write control bit.
2. Read/write of timer A
Stop timer A to read/write its data in the following state;
X
and 6 of CPU mode register (address 3B
cillator output is selected as the timer A count source.
3. Read/write of timer B
Stop timer B to read/write its data in the following state;
X
timer A underflow is selected as the timer B count source, and the
on-chip oscillator output is selected as the timer A count source.
IN
IN
sion ratio is 1/(n+1).
stop a count of the timer.
oscillation selected by clock division ratio selection bits (bits 7
oscillation selected by clock division ratio selection bits, the
0
0
0
IN
pin input signal.
interrupt active edge depends on the CNTR
interrupt request bit is set to “1” at the rising edge of
0
) (frequency not divided) can be selected by the timer X
interrupt active edge selection
OUT
pin is used, set the direction register of port P0
16
)) only when the ceramic oscillation or the
0
OUT
pin input signal. When this bit is “1”, the
pin, to output.
0
interrupt request bit is set to “1” at
4
4
, which is also used as CNTR
, which is also used as CNTR
16
)), and the on-chip os-
0
16
active edge
)).
3
0
0
,