M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 55

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
(2) Asynchronous Serial I/O2 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O2 mode selection bit of the serial I/O2 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Fig. 65 Block diagram of UART serial I/O2
Rev.3.03
REJ03B0006-0303
Fig. 66 Operation of UART serial I/O2 function
Transmit or receive clock
Serial output T
P0
P0
Serial input R
Transmit buffer 2
P0
Receive buffer 2
Notes
4
6
/R
/S
5
write signal
/T
read signal
X
CLK2
X
Jul 11, 2008
D
X
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
D
2
IN
2
interrupt source selection bit (TIC) of the serial I/O2 control register.
X
X
D
D
2
2
ST detector
BRG count source selection bit
TBE=0
1/4
TSC=0
TBE=1
Character length selection bit
Character length selection bit
Page 53 of 117
ST
ST
7 bits
8 bits
Serial I/O2 synchronous clock selection bit
OE
D
D
0
0
Address 002E
TBE=0
D
D
1
1
PE FE
Receive shift register 2
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer register 2
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Data bus
Baud rate generator 2
Data bus
16
Transmit buffer register 2
Transmit shift register 2
SP detector
Address 0032
Address
Serial I/O2 control register
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
1/16
16
RBF=1
SP
SP
TBE=1
Clock control circuit
002E
16
ST
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST
Transmit interrupt source selection bit
Serial I/O2 status register
D
0
D
0
RBF=0
Address 0030
D
D
1
1
1/16
Transmit buffer empty flag (TBE)
Generated at 2nd bit in 2-stop-bit mode
Transmit shift completion flag (TSC)
UART2 control register
Transmit interrupt request (TI)
16
Address
Address 0031
002F
16
TSC=1
SP
RBF=1
SP
16