M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 69

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
Rev.3.03
REJ03B0006-0303
Fig. 86 State transition 2
Operation clock source: f(X
Notes on switch of clock
(1) In operation clock = f(X
(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.
(3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing X
(4) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’,
(5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected.
(6) STP instruction cannot be used when oscillation stop detection circuit is in active.
f(X
f(X
f(X
R
R
R
R
R
Accordingly, do not execute the transition to state 2'a.
OSC
OSC
OSC
OSC
OSC
State 2
State 2’
Oscillation stop detection circuit is in active. (Note 6)
IN
IN
IN
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG
Internal RESET occurs.
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG
Internal RESET does not occur.
Prohibitive state
MUC will be locked when Ceramic
or RC oscillation is stopped.
State 2’a (Note 5)
State 2’b
)/2 (High-speed mode)
)/8 (Middle-speed mode)
) (Double-speed mode, only at a ceramic oscillation)
/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.
/1 (On-chip oscillator double-speed mode)
/2 (On-chip oscillator high-speed mode)
/8 (On-chip oscillator middle-speed mode)
/128 (On-chip oscillator low-speed mode)
Jul 11, 2008
MISRG
MISRG
3
3
is set to “1”.
is set to “1”.
f(X
On-chip oscillator: enabled
f(X
On-chip oscillator: enabled
1
=1
2
=1
IN
IN
2
) oscillation: enabled
) oscillation: enabled
2
MISRG
MISRG
(MISRG
IN
), the following can be selected for the CPU clock division ratio.
Page 67 of 117
2
1
3
=0
IN
=0
is cleared to “0”.)
2
) (Note 1)
2
CPUM
CPUM
CPUM
CPUM
CPUM
CPUM
(Note 4)
(Note 3)
(Note 4)
76
76
76
76
76
76
=10
=00
=00
=10
=00
=10
01
11
01
11
01
11
2
2
2
2
2
2
2
2
2
2
2
2
State 3
State 3’
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG
Internal RESET does not occur.
State 3’b
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG
Internal RESET occurs.
State 3’a
Release from internal reset
MISRG
Oscillation status can be
confirmed by reading MISRG
State 3’c
MISRG
MISRG
3
3
(Note 3)
is set to “1”.
is set to “1”.
3
f(X
On-chip oscillator: enabled
f(X
On-chip oscillator: enabled
is set to “1”.
1
2
IN
=1
=1
IN
IN
) oscillation: enabled
Operation clock source: On-chip oscillator (Note 2)
2
) oscillation: enabled
2
oscillation.
MISRG
(MISRG
MISRG
1
2
3
=0
=0
is cleared to “0”.)
2
2
3
.
Oscillation stop is detected
(internal reset)
Reset
released
(Note 4)
Reset
released
(Note 4)
RESET state 1
f(X
On-chip oscillator: enabled
RESET state 2
f(X
On-chip oscillator: enabled
Applied “L” to RESET pin
(external reset)
MISRG
IN
IN
) oscillation: enabled
) oscillation: enabled
3
is cleared to “0”.