MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 50
Manufacturer Part Number
IC MCU 8BIT 3MHZ 52-PLCC
Specifications of MC68HC11E0CFNE3
Number Of I /o
Program Memory Type
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
No. Of I/o's
Ram Memory Size
No. Of Timers
Embedded Interface Type
Digital Ic Case Style
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
Lead Free Status / Rohs Status
5.3 Reset and Interrupt Priority
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis-
ter is clear, and disabled if NOCOP is set. The COP rate is set for the shortest duration
The reset condition of the SCI system is independent of the operating mode. At reset,
the SCI baud rate is indeterminate and must be established by a software write to the
BAUD register. All transmit and receive interrupts are masked and both the transmitter
and receiver are disabled so the port pins default to being general-purpose I/O lines.
The SCI frame format is initialized to an 8-bit character size. The send break and re-
ceiver wake-up functions are disabled. The TDRE and TC status bits in the SCI status
register are both set, indicating that there is no transmit data in either the transmit data
register or the transmit serial shift register. The RDRF, IDLE, OR, NF, and FE receive-
related status bits are cleared.
The SPI system is disabled by reset. The port pins associated with this function default
to being general-purpose I/O lines.
The memory system is configured for normal read operation. PSEL[3:0] are initialized
with the value $0101, causing the external IRQ pin to have the highest I-bit interrupt
priority. The IRQ pin is configured for level sensitive operation (for wired-OR systems).
The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the
MODB and MODA inputs at the rising edge of reset. The DLY control bit in OPTION is
set to specify that an oscillator start-up delay is imposed upon recovery from STOP.
The clock monitor system is disabled by CME equals zero.
Resets and interrupts have a hardware priority that determines which reset or interrupt
is serviced first when simultaneous requests occur. Any maskable interrupt can be giv-
en priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is as follows:
1. POR or RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
Freescale Semiconductor, Inc.
For More Information On This Product,
RESETS AND INTERRUPTS
Go to: www.freescale.com