SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet - Page 28

• Manufacturer Part Number: SAK-TC1775-L40E BA
• Description: IC MCU 32BIT 40MHZ BGA-329
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1775-L40E BA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SDLM, SSC, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 176
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: ROM
• Ram Size: 73K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.75 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 329-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: SAKTC1775L40EBA; SP000012965

Preliminary
Each ASC module, ASC0 and ASC1, communicates with the external world via two pairs
of two I/O lines each. The RXD line is the receive data input signal (in Synchronous Mode
also output). TXD is the transmit output signal. Clock control, address decoding, and
interrupt service request control are managed outside the ASC module kernel.
The Asynchronous/Synchronous Serial Interfaces provide serial communication
between the TC1775 and other microcontrollers, microprocessors or external
peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data are double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal that can be very accurately adjusted
by a prescaler implemented as a fractional divider.
Features:
• Full duplex asynchronous operating modes
• Half-duplex 8-bit synchronous operating mode
• Double buffered transmitter/receiver
• Interrupt generation
• Two pin pairs RXD/TXD for each ASC available at Port 12 or Port 13
Data Sheet
– 8-bit or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
– Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock)
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
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V1.2, 2002-05
TC1775