SAK-TC1775-L40E BA Infineon Technologies, SAK-TC1775-L40E BA Datasheet - Page 54

• Manufacturer Part Number: SAK-TC1775-L40E BA
• Description: IC MCU 32BIT 40MHZ BGA-329
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1775-L40E BA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SDLM, SSC, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 176
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: ROM
• Ram Size: 73K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.75 V
• Data Converters: A/D 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 329-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: SAKTC1775L40EBA; SP000012965

Preliminary
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1775 in a user-specified time period. When enabled, the WDT will
cause the TC1775 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1775 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the EndInit
feature and monitors its modifications. A system-wide line is connected to the ENDINIT
bit implemented in a WDT control register, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection).
A further enhancement in the TC1775’s Watchdog Timer is its reset prewarning
operation. Instead of immediately resetting the device on the detection of an error, as
known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI)
to the CPU before finally resetting the device at a specified time period later. This gives
the CPU a chance to save system state to memory for later examination of the cause of
the malfunction, an important aid in debugging.
Features:
• 16-bit Watchdog counter
• Selectable input frequency:
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated password access mechanism with fixed and user-definable password
• Proper access always requires two write accesses. The time between the two
• Access Error Detection: Invalid password (during first access) or invalid guard bits
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
• Watchdog function can be disabled; access protection and ENDINIT monitor function
• Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
Data Sheet
for Time-Out and Prewarning Modes
fields
accesses is monitored by the WDT and limited.
(during second access) trigger the Watchdog reset generation.
generation.
remain enabled.
access to its control register in between, a severe system malfunction is assumed and
the TC1775 is held in reset until a power-on reset. This prevents the device from being
periodically reset if, for instance, connection to the external memory has been lost
such that even system initialization could not be performed.
f
SYS
/256 or
f
50
SYS
/16384
V1.2, 2002-05
TC1775