ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 139

• Manufacturer Part Number: ATA5771-PXQW
• Description: XMITTR UHF ASK/FSK 868MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5771-PXQW

• Frequency: 868MHz ~ 928MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.19.2.3
9137E–RKE–12/10
DIDR0 – Digital Input Disable Register 0
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to
the input capture front-end logic, making the comparator utilize the noise canceler and edge
select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no con-
nection between the Analog Comparator and the input capture function exists. To make the
comparator trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer
Interrupt Mask Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in
Table 4-47.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when
the bits are changed.
• Bits 1, 0 – ADC0D,ADC1D: ADC 1/0 Digital input buffer disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The cor-
responding PIN Register bit will always read as zero when this bit is set. When an analog
signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit
should be written logic one to reduce power consumption in the digital input buffer.
Bit
0x01 (0x21)
Read/Write
Initial Value
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ADC7D
R/W
7
0
ACIS0
0
1
0
1
ADC6D
R/W
6
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
ADC5D
R/W
5
0
Table
ADC4D
4-47.
R/W
4
0
ADC3D
R/W
3
0
Atmel ATA5771/73/74
ADC2D
R/W
2
0
ADC1D
R/W
1
0
ADC0D
R/W
0
0
DIDR0
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