ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 173

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Internal Clock
Generation – The
Baud Rate Generator
Double Speed
Operation (U2X)
2467V–AVR–02/11
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRR+1)). The transmitter divides the
baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator
output is used directly by the receiver’s clock and data recovery units. However, the recovery
units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 74
the UBRR value for each mode of operation using an internally generated clock source.
Table 74. Equations for Calculating Baud Rate Register Setting
Note:
Some examples of UBRR values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
Operating Mode
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed
Mode (U2X = 1)
Synchronous Master Mode
txclk
rxclk
xcki
xcko
fosc
BAUD Baud rate (in bits per second, bps)
f
UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)
OSC
193).
1. The baud rate is defined to be the transfer rate in bit per second (bps).
contains equations for calculating the baud rate (in bits per second) and for calculating
Transmitter clock. (Internal Signal)
Receiver base clock. (Internal Signal)
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
System Oscillator clock frequency
BAUD
BAUD
BAUD
Equation for Calculating
Baud Rate
=
=
=
-------------------------------------- -
16 UBRR
---------------------------------- -
8 UBRR
---------------------------------- -
2 UBRR
(
(
(
f
f
f
Figure
OSC
OSC
OSC
(1)
+
+
+
1
1
1
80.
)
)
)
Equation for Calculating
UBRR
UBRR
UBRR
UBRR Value
=
=
=
----------------------- - 1
16BAUD
ATmega128
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
Table 82
(see
173

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