ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL
Quantity:
3 645
Part Number:
ATMEGA128RFA1-ZUR
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Quantity:
56 000
8266A-MCU Wireless-12/09
Features
• High Performance, Low Power AVR
• Advanced RISC Architecture
• Non-volatile Program and Data Memories
• JTAG (IEEE std. 1149.1 compliant) Interface
• Peripheral Features
• Advanced Interrupt Handler
• Watchdog Timer with Separate On-Chip Oscillator
• Power-on Reset and Low Current Brown-Out Detector
• Advanced Power Save Modes
• Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
• Hardware Security (AES, True Random Generator)
• Integrated Crystal Oscillators (32.768 kHz & 16 MHz)
• I/O and Package
• Temperature Range: -40° C to 85° C Industrial
• Supply voltage range 1.8V to 3.6V with integrated voltage regulators
• Ultra Low Power consumption (1.8 to 3.6V) for Rx/Tx & AVR: <18.6 mA
• Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V
Applications
• ZigBee
• General Purpose 2.4GHz ISM Band Transceiver with Microcontroller
• RF4CE, SP100, WirelessHART
- 135 Powerful Instructions – Most Single Clock Cycle Execution
- 32x8 General Purpose Working Registers
- Fully Static Operation
- Up to 16 MIPS Throughput at 16 MHz and 1.8V
- On-Chip 2-cycle Multiplier
- 128K Bytes of In-System Self-Programmable Flash
- 4K Bytes EEPROM
- 16K Bytes Internal SRAM
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug Support
- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface
- Multiple Timer/Counter & PWM channels
- Real Time Counter with Separate Oscillator
- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor
- Master/Slave SPI Serial Interface
- Two Programmable Serial USART
- Byte Oriented 2-wire Serial Interface
- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm
- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
- 32 Bit IEEE 802.15.4 Symbol Counter
- Baseband Signal Processing
- SFR-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation
- Antenna Diversity and TX/RX control
- TX/RX 128 Byte Frame Buffer
- 38 Programmable I/O Lines
- 64-pad QFN (RoHS/Fully Green)
- CPU Active Mode (16MHz): 4.1 mA
- 2.4GHz Transceiver: RX_ON 12.5 mA / TX 14.5 mA (maximum TX output power)
- Deep Sleep Mode: <250nA @ 25° C
• Endurance: 2000 Write/Erase Cycles @ 85° C
• Endurance: 2000 Write/Erase Cycles @ 85° C
®
/ IEEE 802.15.4-2006/2003
, ISM Applications and IPv6 / 6LoWPAN
®
8-Bit Microcontroller
– Full And Reduced Function Device (FFD/RFD)
ATmega128RFA1
8-bit
Microcontroller
with Low Power
2.4GHz
Transceiver for
ZigBee and
IEEE 802.15.4
ATmega128RFA1
PRELIMINARY
8266A-MCU Wireless-12/09
1

Related parts for ATMEGA128RFA1-ZU

ATMEGA128RFA1-ZU Summary of contents

Page 1

... General Purpose 2.4GHz ISM Band Transceiver with Microcontroller ™ • RF4CE, SP100, WirelessHART 8266A-MCU Wireless-12/09 ® 8-Bit Microcontroller ™ – Full And Reduced Function Device (FFD/RFD) , ISM Applications and IPv6 / 6LoWPAN ATmega128RFA1 8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4 ATmega128RFA1 PRELIMINARY 8266A-MCU Wireless-12/09 1 ...

Page 2

... Pin Configurations [PF2:ADC2:DIG2] [PF3:ADC3:DIG4] [PF4:ADC4:TCK] [PF5:ADC5:TMS] [PF6:ADC6:TDO] [PF7:ADC7:TDI] [AVSS_RFP] [AVSS_RFN] [RSTN] [RSTON] [PG0:DIG3] [PG1:DIG1] [PG2:AMR] 2 Disclaimer ATmega128RFA1 2 Figure 1-1. Pinout ATmega128RFA1 Index corner ATmega128RFA1 7 [RFP] 8 [RFN [TST Exposed paddle: [AVSS Note: The large center pad underneath the QFN/MLF package is made of metal and internally connected to AVSS ...

Page 3

... Overview 3.1 Block Diagram 8266A-MCU Wireless-12/09 The ATmega128RFA1 is a low-power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz ISM band derived from the ATmega1281 microcontroller and the AT86RF231 radio transceiver. ...

Page 4

... Spectrum Signal (DSSS) processing with spreading and despreading. The device is fully compatible with IEEE802.15.4-2006/2003 and ZigBee standards. The ATmega128RFA1 provides the following features: 128 kbytes of In-System Programmable (ISP) Flash with read-while-write capabilities, 4 kbytes EEPROM, 16 kbytes SRAM general purpose I/O lines, 32 general purpose working ...

Page 5

... Read-While-Write operation. By combining an 8 bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128RFA1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128RFA1 AVR is supported with a full suite of program and system development tools including: debugger/simulators, in-circuit emulators, and evaluation kits. External analog supply voltage ...

Page 6

... Reference voltage output of the A/D Converter. In general this pin is left open. Programming and test mode enable pin; Input to the clock system. If selected, it provides the operating clock of the microcontroller. The basic AVR feature set of the ATmega128RFA1 is derived from the ATmega1281/2561. Address locations and names of the implemented modules and , higher while the ...

Page 7

... XTAL1 and XTAL2. An external clock can be applied to the microcontroller using the clock input CLKI. The ATmega128RFA1 has a new A/D converter. Software compatibility is basically assured. Nevertheless to benefit from the higher conversion speeds and the better performance some changes are required. ...

Page 8

... ATmega128RFA1 8 • over 10 years at 85° C • TBD years at 25°C. 8266A-MCU Wireless-12/09 ...

Page 9

... While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATmega128RFA1 Data Bus 8-bit Status and Control ...

Page 10

... Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega128RFA1 has Extended I/O space from 0x60 - 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

Page 11

... The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. • Bit 0 – Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically ATmega128RFA1 ...

Page 12

... General Purpose Register File 7.5.1 The X-register, Y-register, and Z-register ATmega128RFA1 12 stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • ...

Page 13

... The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. • Bit 7:0 – SP15:8 - Stack Pointer High Byte ATmega128RFA1 ...

Page 14

... SPL – Stack Pointer Low 7.6.3 RAMPZ – Extended Z-pointer Register for ELPM/SPM ATmega128RFA1 14 Bit $3D ($5D) SP7 SP6 SP5 Read/Write Initial Value The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed ...

Page 15

... Boot Flash section by programming the BOOTRST Fuse, see "Memory Programming" on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested ATmega128RFA1 " ...

Page 16

... ATmega128RFA1 16 interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag ...

Page 17

... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set. ATmega128RFA1 17 ...

Page 18

... Boot Program section and Application Program section. The Flash memory has an endurance of at least 2000 write/erase cycles. The ATmega128RFA1 Program Counter (PC bits wide, thus addressing the required program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Read-While-Write Self-Programming" ...

Page 19

... When using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM in the ATmega128RFA1 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page Figure 8-7 ...

Page 20

... Data RD Memory Access Instruction The ATmega128RFA1 contains 4Kbyte of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 2000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

Page 21

... Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write ATmega128RFA1 21 ...

Page 22

... Preventing EEPROM Corruption ATmega128RFA1 22 Assembly Code Example sbic EECR,EEPE rjcmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) ...

Page 23

... For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. • Bit 7:0 – EEDR7:0 - EEPROM Data ATmega128RFA1 ...

Page 24

... EECR – EEPROM Control Register ATmega128RFA1 24 Bit $1F ($3F) Res1 Res0 EEPM1 Read/Write Initial Value • Bit 7:6 – Res1:0 - Reserved • Bit 5:4 – EEPM1:0 - EEPROM Programming Mode The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE possible to program data in one atomic operation (erase the old value and program the new value split the Erase and Write operations in two different operations ...

Page 25

... The Input/Output (I/O) space definition of the ATmega128RFA1 is shown in Summary" on page 496. All ATmega128RFA1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 – ...

Page 26

... Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value The inherited control registers of missing ports located in the I/O space are kept in the ATmega128RFA1. They can be used as general purpose I/O registers for storing any information. Registers placed in the address range 0x00 – 0x1F are directly bit- accessible using the SBI, CBI, SBIS and SBIC instructions ...

Page 27

... The PINA register is reserved for interal use and cannot be used as a General Purpose I/O Register. • Bit 7:0 – PINA7:0 - Port A Input Pins Bit $08 ($28) Read/Write Initial Value The PORTC register can be used as a General Purpose I/O Register for storing any information. • Bit 7:0 – PORTC7:0 - Port C Data Register Value ATmega128RFA1 PORTA7 ...

Page 28

... DDRC – Port C Data Direction Register 8.7.6 PINC – Port C Input Pins Address ATmega128RFA1 28 Bit $07 ($27) DDC7 DDC6 DDC5 Read/Write Initial Value The DDRC register can be used as a General Purpose I/O Register for storing any information. • Bit 7:0 – DDC7:0 - Port C Data Direction Register Value ...

Page 29

... RX/TX indication (external RF front-end control antenna diversity o Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s o True random number generation for security applications o • Compliant to IEEE 802.15.4-2006, IEEE 802.15.4-2003 and RF4CE • Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210 ATmega128RFA1 29 ...

Page 30

... Analog Domain ATmega128RFA1 30 The ATmega128RFA1 features a low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true peripheral block of the AVR microcontroller. All RF-critical components except the antenna, crystal and de- coupling capacitors are integrated on-chip ...

Page 31

... Depending on the controller clock speed, program execution wait cycles are generated. That means if the controller runs with about 16MHz or faster, at least three wait cycles are generated, but if the controller runs with about 4MHz, no wait cycles are inserted. A ATmega128RFA1 [1] on page 100 85, are provided to simplify the interaction between ...

Page 32

... Frame Buffer Access 9.3.1.3 Transceiver Pin Register TRXPR ATmega128RFA1 32 register access is only possible, if the transceiver clock is available. Therefore the transceiver must be enabled (PRR1 Register) and not in SLEEP state. The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802 ...

Page 33

... Interrupts are not cleared automatically when the event that caused them vanishes. More information about interrupt handling by the controller can be found in section "Interrupts" on page 211. The supported interrupts for the Basic Operating Mode are summarized in page 34. ATmega128RFA1 35. Table 9 ...

Page 34

... The interrupt handling in Extended Operating Mode is described in section Handling" on page 59. The ATmega128RFA1 Transceiver module can be identified by four registers (PART_NUM, VERSION_NUM, MAN_ID_0, MAN_ID_1). One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JTAG manufacture ID. The transceiver identification registers are provided for compatibility to the transceiver only device ...

Page 35

... TRXRST of the TRXPR register. A successful state change can be verified by reading the radio transceiver status from register TRX_STATUS. If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the radio transceiver state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. ATmega128RFA1 Table 9-3 on page 42 ...

Page 36

... Basic Operating Mode Description 9.4.1.2.1 SLEEP – Sleep State 9.4.1.2.2 TRX_OFF – Clock State ATmega128RFA1 36 Bit SLPTR is a multifunctional bit (refer to section page 32 for more details). Dependent on the radio transceiver state, a “0” to “1” transition on SLPTR causes the following state transitions: • ...

Page 37

... This mode is for legacy operation and should be replaced by the TX_START command below. • TX_START command to bits TRX_CMD of register TRX_STATE. Either of these causes the radio transceiver into the BUSY_TX state. ATmega128RFA1 "Frame Filtering" 33. The expected address values are to be "Frame Filtering" on ...

Page 38

... The RESET state is used to set back the state machine and to reset all registers of the radio transceiver to their default values. A reset forces the radio transceiver into the TRX_OFF state. A reset is initiated by a ATmega128RFA1 main reset (see 176 radio transceiver reset (see During radio transceiver reset the TRXPR register is not cleared and therefore the application software has to set the SLPTR bit to “ ...

Page 39

... XOSC startup Tim e The radio transceiver SLEEP state is left by releasing bit SLPTR to “0”. This restarts the XOSC not already running. After t page 42) the radio transceiver enters TRX_OFF state. If the XOSC is already running, the radio transceiver enters TRX_OFF state after 25 µs. ATmega128RFA1 ...

Page 40

... PLL_ON and RX_ON States 9.4.1.4.3 BUSY_TX and RX_ON States ATmega128RFA1 40 During this wake-up procedure the calibration of the filter-tuning network (FTN) is performed. Entering TRX_OFF state is signaled by the TRX24_AWAKE interrupt, if enabled. The transition from TRX_OFF to PLL_ON and RX_ON mode is shown in below. Figure 9-15. Transition from TRX_OFF to PLL_ON and RX_ON State ...

Page 41

... TRX_OFF, do not try to initiate a further state change while the radio transceiver is in this state. Note that before accessing the radio transceiver module the TRX24_AWAKE event should be checked. ATmega128RFA1 = state PLL_ON. TR11 Figure 9-17 below. ...

Page 42

... TR19 20 t PLL, settling TR20 21 t PLL, CF cal TR21 22 t PLL, DCU cal TR22 23 t PLL TR23 ATmega128RFA1 42 The transition numbers correspond to "Basic Application Schematic" on page 493. Time [µs], (typ) TRX_OFF 240 SLEEP 35 · CLKM PLL_ON 110 TRX_OFF 1 RX_ON 110 TRX_OFF 1 ...

Page 43

... An ACK received in TX_ARET mode within the time required by IEEE 802.15.4 is accepted if the FCS is valid and if the sequence number of the ACK matches the sequence number of the previously transmitted frame. Dependent on the value of the ATmega128RFA1 Maximum PLL settling time TX RX RSSI update period in receive states, refer to RSSI" ...

Page 44

... tec ran tio ATmega128RFA1 44 frame pending subfield in the received acknowledgement frame the transaction status is set according to Table 9-16 on page 58. The state diagram including the Extended Operating Mode states is shown in 18 below. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode ...

Page 45

... When using the RX_AACK or TX_ARET modes, the following registers needs to be configured. RX_AACK configuration steps: • Short address, PAN-ID SHORT_ADDR_1, PAN_ID_0, PAN_ID_1, IEEE_ADDR_0 … IEEE_ADDR_7) • Configure RX_AACK properties (register XAH_CTRL_0, CSMA_SEED_1) Handling of Frame Version Subfield o ATmega128RFA1 35. and IEEE address (register Figure 9-18 on SHORT_AADR_0, 45 ...

Page 46

... RX_AACK_ON – Receive with Automatic ACK ATmega128RFA1 46 Handling of Pending Data Indicator o Characterize as PAN coordinator o Handling of Slotted Acknowledgement o • Additional Frame Filtering Properties (register XAH_CTRL_1, CSMA_SEED_1) Promiscuous Mode o Enable or disable automatic ACK generation o Handling of reserved frame types o The addresses for the address match algorithm are to be stored in the appropriate address registers ...

Page 47

... MAC hardware accelerator in promiscuous mode (see section "Configuration of non IEEE 802.15.4 Compliant Scenarios" on The status of the RX_AACK operation is indicated by the bits TRAC_STATUS of register TRAC_STATUS. During the operations described BUSY_RX_AACK state. ATmega128RFA1 page 50). In that case a page 52). above the radio transceiver remains in ...

Page 48

... Note 2: FCS check is omitted for Promiscous Mode Note 3: Additional conditions: - ACK requested & - ACK_DIS_ACK==0 & - frame_version<=AACK_FVN_MODE N AACK_ACK_TIME Wait 2 symbol Wait 6 symbol periods SLPTR bit = 1 Y ATmega128RFA1 48 TRX_STATE = RX_AACK_ON N SHR detected Y TRX_STATE = BUSY_RX_AACK Generate TRX24_RX_START interrupt Scanning MHR N Frame Filtering (see Note 1) ...

Page 49

... RX_AACK mode (see Feature Set" on page 85). Each of these operating modes can be combined with the RX_AACK mode. ATmega128RFA1 Description Set node addresses Protect buffer after frame receive Support promiscuous mode Change auto acknowledge start time ...

Page 50

... Configuration of IEEE Scenarios ATmega128RFA1 50 Normal Device The Table 9-6 below shows a typical RX_AACK configuration of an IEEE 802.15.4 device operated as a normal device rather than a PAN coordinator or router. Table 9-6. Configuration of IEEE 802.15.4 Devices Register Name Register Bits SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … ...

Page 51

... SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 AACK_PROM_MODE 1 AACK_DIS_ACK 4 ATmega128RFA1 Description Set node addresses 0: disable frame protection 1: enable frame protection 0: if transceiver works in unslotted mode 1: if transceiver works in slotted mode 1: device is PAN coordinator 0: frame pending subfield is not set in FCF 1: frame pending subfield is set in FCF ...

Page 52

... Configuration of non IEEE 802.15.4 Compliant Scenarios ATmega128RFA1 52 Register Name Register Bits AACK_FVN_MODE 7:6 Second level of filtering according to IEEE 802.15.4-2006, section 7.5.6.2, is applied to a received frame if the radio transceiver is in promiscuous mode. However, a TRX24_RX_END interrupt is issued even if the FCS is invalid. Thus it is necessary to read bit RX_CRC_VALID of register PHY_RSSI after the TRX24_RX_END interrupt in order to verify the reception of a frame with a valid FCS ...

Page 53

... Any non-corrupted frame with a reserved frame type is indicated by a TRX24_RX_END interrupt. No further address filtering is applied on those frames. A TRX24_AMI interrupt is never generated and the acknowledgment subfield is ignored. 2. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 1: ATmega128RFA1 Table 9-16 on page 63) can also be Description Set node addresses 0: disable frame protection ...

Page 54

... Frame Filtering ATmega128RFA1 54 If AACK_FLT_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. Consequently, a TRX24_AMI interrupt is generated upon address match. A TRX24_RX_END interrupt is only generated if the address matched and the frame was not corrupted ...

Page 55

... MAC command frame. The transmission of the acknowledgement frame is initiated by the microcontroller by writing SLPTR=1 and starts 16µ specified in section "Digital Interface Timing Characteristics" on page IRQ ATmega128RFA1 Figure 9-26 on page 63. This effectively by register bits AACK_FLTR_RES_FT ...

Page 56

... Processing D elay 9.4.2.4.2 RX_AACK Mode Timing Figure 9-11. Example Timing of an RX_AACK Transaction ram e T ype yp. P rocessing D elay ATmega128RFA1 ata Fram e (Length = 10 _AA sym bols) w aiting period signaled by register bits bit AACK_ACK_TIME of register XAH_CTRL_1 is set, an acknowledgment frame can be sent already 2 symbol times after the reception of the last symbol of a data or MAC command frame ...

Page 57

... TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry Figure 9-12. Flow Diagram of TX_ARET fra rctr = MAX_CSM A_RETRIES < rctr = rctr + fra fra rctr + ste til tim lid N N fra > 8266A-MCU Wireless-12/ try rfo rctr > ilu re MAX_CSMA_RETRIES rru ATmega128RFA1 ...

Page 58

... ATmega128RFA1 58 Overview The implemented TX_ARET algorithm is shown in In TX_ARET mode, the radio transceiver first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply ...

Page 59

... Mode (see section "Interrupt Handling" on interrupts by setting the appropriate bit in register IRQ_MASK. For RX_AACK and TX_ARET the following interrupts about the status of a frame reception and transmission: ATmega128RFA1 Description No acknowledgement frames were received during all retry attempts Entering TX_ARET mode sets ...

Page 60

... Register Summary ATmega128RFA1 60 Table 9-13. Interrupt Handling in Extended Operating Mode Mode Interrupt RX_AACK TRX24_RX_START TRX24_AMI TRX24_RX_END TX_ARET TRX24_TX_END Both TRX24_PLL_LOCK RX_AACK For RX_AACK it is recommended to enable the TRX24_RX_END interrupt. This interrupt is issued only if a frame passes the frame filtering (see section Filtering" ...

Page 61

... The PHY header is a single octet following the SHR. The least significant 7 bits denote the frame length of the following PSDU, while the most significant bit of that octet is reserved, and shall be set to 0 for IEEE 802.15.4 compliant frames. ATmega128RFA1 shows the frame structure of the 61 ...

Page 62

... MAC Protocol Layer Data Unit (MPDU) Figure 9-15. IEEE 802.15.4 Frame Format - MAC-Layer Frame Structure (MPDU) 9.5.1.2.1 MAC Header (MHR) Fields ATmega128RFA1 62 On receive the PHR is returned as the first octet during Frame Buffer read access. Even though the standard only defines frame lengths 127 bytes, the radio transceiver is able to transmit and receive frame length values > ...

Page 63

... The radio transceiver parses this bit during RX_AACK mode and transmits an acknowledgment frame if necessary. In TX_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the case, the receiver waits for the acknowledgment frame, otherwise the TX_ARET transaction is finished. ATmega128RFA1 Table 9-16 below summarizes frame types defined Description Beacon ...

Page 64

... ATmega128RFA1 64 Bit 6: the “Intra-PAN” subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address filed is omitted. In RX_AACK mode this bit is evaluated by the address filter logic of the radio transceiver. Bit [11:10]: the “Destination Addressing Mode” subfield describes the format of the destination address of the frame ...

Page 65

... The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see IEEE 802.15.4-2006, 7.6.1). This field shall be present only if the Security Enabled ATmega128RFA1 with a MAC ...

Page 66

... MAC Service Data Unit (MSDU) 9.5.1.2.8 MAC Footer (MFR) Fields 9.5.2 Frame Check Sequence (FCS) 9.5.2.1 Overview 9.5.2.2 CRC calculation ATmega128RFA1 66 subfield b3 is set to one (see section 2003 and IEEE 802.15.4-2006" on IEEE 802.15.4-2006, 7.6.2 Auxiliary security header. This is the actual MAC payload usually structured according to the individual frame type ...

Page 67

... Minimum RSSI value is 0; • Maximum RSSI value is 28. The RSSI is a 5-bit value indicating the receive power in the selected channel in steps of 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others. Only the ATmega128RFA1 N 127), the FCS is calculated on the 2. ...

Page 68

... Reading RSSI 9.5.3.3 Data Interpretation 9.5.4 Energy Detection (ED) 9.5.4.1 Overview ATmega128RFA1 68 received signal strength is evaluated. The RSSI provides the basis for an ED measurement. See section "Energy Detection (ED)" below In Basic Operating Mode the RSSI value is valid in any receive state, and is updated every register PHY_RSSI ...

Page 69

... ED value has a maximum tolerance of ±5 dB, this considered as constant offset over the measurement range value of 0 indicates an RF input power of P range 84, the RF input power can be calculated as follows: ATmega128RFA1 86. The measurement period in = 140 µs (128 µs measurement duration TR26 508). Due to environmental conditions (temperature, -90 dBm ...

Page 70

... Interrupt Handling 9.5.5 Clear Channel Assessment (CCA) 9.5.5.1 Overview ATmega128RFA1 - [dBm] RF Figure 9-18. Mapping between values in PHY_ED_LEVEL and Received Input Power 10 0 Measured -10 Ideal -20 -30 -40 -50 -60 -70 -80 -90 -100 The TRX24_CCA_ED_DONE interrupt is issued at the end of a manually initiated ED measurement. Note that an ED request should only be initiated in one of the receive states. Otherwise the radio transceiver generates a TRX24_CCA_ED_DONE interrupt but no ED measurement was performed ...

Page 71

... The TRX24_CCA_ED_DONE interrupt is issued at the end of a manually initiated CCA measurement. Note: A CCA request should only be initiated in the receive states of Basic Operating Mode. Otherwise the radio transceiver generates a TRX24_CCA_ED_DONE interrupt and sets the register bit CCA_DONE = 1 even if no CCA measurement was performed. ATmega128RFA1 CCA measurement is indicated "Transceiver Electrical ...

Page 72

... Measurement Time 9.5.6 Link Quality Indication (LQI) 9.5.6.1 Overview ATmega128RFA1 72 The response time for a manually initiated CCA measurement depends on the receiver state. In RX_ON state the CCA measurement is done over eight symbol periods and the result is accessible 140 µs after the request (see section Request" ...

Page 73

... According to IEEE 802.15.4 a low LQI value is associated with low signal strength and/or high signal distortions. Signal distortions are mainly caused by interference signals and/or multipath propagation. High LQI values indicate a sufficient high signal power and low signal distortions. ATmega128RFA1 100 150 200 ...

Page 74

... PPF R FN ATmega128RFA1 74 Note that the received signal power as indicated by the received signal strength indication (RSSI) value or energy detection (ED) value of the radio transceiver do not characterize the signal quality and the ability to decode a signal example, a received signal with an input power of about 6 dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions ...

Page 75

... The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with bit RX_PDT_DIS of register RX_SYN set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is detected until the register bit RX_PDT_DIS is set back. ATmega128RFA1 35), the reception of a "Extended Operating "Frame Receive Procedure" on page " ...

Page 76

... D IG3 Buf R FN 9.6.2.2 Frame Transmit Procedure 9.6.2.3 Configuration 9.6.2.4 TX Power Ramping ATmega128RFA1 76 The transmitter consists of a digital base band processor (TX BBP) and an analog front end as shown in the following figure. Ext front-end and Output Power C ontrol PLL – odulation TX D ata ...

Page 77

... The state of the radio transceiver should be changed to PLL_ON state after reception to protect the Frame Buffer content against overwriting with new, incoming frames. This can be achieved by writing immediately the command PLL_ON to the TRX_CMD bits of register TRX_STATE after receiving the frame indicated by a TRX24_RX_END interrupt. ATmega128RFA1 ...

Page 78

... Preamble Sequence 4 octets / 128 µs Duration SHR not accesible Access PHY generated ATmega128RFA1 78 Alternatively Dynamic Frame Buffer Protection can be used to protect received frames against overwriting. For details refer to Both procedures do not protect the Frame Buffer from overwriting by the application software. In Extended Operating Mode during TX_ARET operation (see Transmit with Automatic Retry and CSMA-CA Retry" ...

Page 79

... The bit BATMON_OK of register BATMON monitors the current value of the battery voltage: • If BATMON_OK = 0 then the battery voltage is lower than the threshold voltage; • If BATMON_OK = 1 then the battery voltage is higher than the threshold voltage; ATmega128RFA1 BATMON_OK + - „1“ ...

Page 80

... Interrupt Handling 9.6.5 Crystal Oscillator (XOSC) 9.6.5.1 Overview 9.6.5.2 Integrated Oscillator Setup ATmega128RFA1 80 The value BATMON_OK should be read out to verify the current supply voltage value after setting a new threshold. Note: The battery monitor is inactive during SLEEP states. Refer to status register TRX_STATUS for details ...

Page 81

... When using an external reference frequency, the signal must be connected to pin XTAL1 as indicated in Figure 9-26 on XOSC_CTRL need to be set to the external oscillator mode. The oscillation peak-to- peak amplitude shall between 100 mV and 500 mV, the optimum range is between 400 mV and 500 mV. Pin XTAL2 should not be wired ATmega128RFA1 . PAR CX C PAR ...

Page 82

... Frequency Synthesizer (PLL) 9.6.6.1 Overview 9.6.6.2 RF Channel Selection 9.6.6.3 Frequency Agility ATmega128RFA1 82 Figure 9-26. Setup for Using an External Frequency Reference 16 MHz XTAL1 The main features of the phase-locked loop are: • Generate RX/TX frequencies for all 2.4 GHz channels of IEEE 802.15.4; ...

Page 83

... RX_ON if necessary. This applies in particular to the High Data Rate Modes with a much higher sensitivity to variations of the BPF transfer function. The recommended calibration interval is 5 min or less. This section describes the basic procedures to receive and transmit frames with the radio transceiver. ATmega128RFA1 "General Circuit Description" on page 83 ...

Page 84

... Frame Receive Procedure 9.7.2 Frame Transmit Procedure ATmega128RFA1 84 A frame reception comprises of two actions: The PHY listens for a frame, receives and demodulates the frame to the Frame Buffer and signalizes its reception to the application software. The application software reads the available frame data from the Frame Buffer after or during the progress of the frame reception ...

Page 85

... Write frame data (Frame Buffer access) IRQ issued (TX_END) The radio transceiver incorporates a 2-bit, noise observing, true random number generator to be used to: • Generate random seeds for CSMA-CA algorithm page 43); ATmega128RFA1 (Register access) Figure 9-29 below. This is applicable for time (Register access) (see"Extended Operating Mode" ...

Page 86

... High Data Rate Modes 9.8.2.1 Overview 9.8.2.2 High Data Rate Packet Structure ATmega128RFA1 86 • Generate random values for AES key generation (see page 92); The random number is updated every t states. The values are stored in bits RND_VALUE of register PHY_RSSI. The main features of the High Data Rate Modes are: • ...

Page 87

... Frame Buffer after the PSDU data is the ED value rather than the LQI value. According to IEEE 802.15.4 the ED measurement duration is 8 symbol periods. For frames operated at higher data rates the automated ED measurement duration is reduced to 32 µs to take the reduced frame length into account (ED)" on page 68). ATmega128RFA1 1000 kbps 500 kbps 250 kbps 40 60 ...

Page 88

... AACK_ACK_TIME = 0 AACK_ACK_TIME = 1 9.8.3 Antenna Diversity 9.8.3.1 Overview ATmega128RFA1 88 Receiver Sensitivity Control The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU) cause a different sensitivity between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. The receiver does not receive frames with an RSSI level below the defined sensitivity threshold level (register bits RX_PDT_LEVEL > ...

Page 89

... Extended Operating Mode. An application software defined selection of a certain antenna can be done by disabling the automatic Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bit ANT_CTRL. ATmega128RFA1 ega 128R ...

Page 90

... Antenna Diversity Sensitivity Control 9.8.4 RX/TX Indicator 9.8.4.1 Overview 9.8.4.2 External RF-Front End Control ATmega128RFA1 90 If the radio transceiver is not in a receive or transmit state recommended to disable register bit ANT_EXT_SW_EN and to set the port pins DIG1 and DIG2 to output low (DDG1 = 1, PORTG1 = 0, DDF2 = 1, PORTF2 = 0) in order to reduce the power consumption or avoid leakage current of the external RF switch especially during sleep modes ...

Page 91

... It is not recommended to set the low-order 4 bits to 0 due to the way the SHR is formed. The ATmega128RFA1 continues the reception of incoming frames as long any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the ...

Page 92

... Security Module (AES) 9.8.8.1 Overview 9.8.8.2 Security Module Preparation ATmega128RFA1 92 Protection prevents that a new valid frame passes to the Frame Buffer until the buffer protection bit is cleared (RX_SAFE_MODE = 0). A received frame is automatically protected against overwriting: • in Basic Operating Mode, if its FCS is valid • ...

Page 93

... All configurations of the security module, the SRAM content and keys are reset during SLEEP or RESET states. The key is stored Byte sequential buffer. To read or write the contents of the buffer, 16 consecutive read or write operations to the AES_KEY register are required. ATmega128RFA1 Description Select AES mode: ECB or CBC Select encryption or decryption ...

Page 94

... Security Operation Modes 9.8.8.4.1 Electronic Code Book (ECB) ATmega128RFA1 94 A 16-folded read access to registers AES_KEY returns the last round key of the preceding security operation. This is the key required for the corresponding ECB decryption operation after an ECB encryption operation. However the initial AES key ...

Page 95

... However any other initialization vector can be applied for non-compliant usage. This operation has to be prepared by the application software. Note that the MIC algorithm of the IEEE 802.15.4-2006 standard requires CBC mode encryption only because it implements a one-way hash function. ATmega128RFA1 Plaintext Encryption Block Cipher Key ...

Page 96

... AES Interrupt Handling 9.9 Continuous Transmission Test Mode 9.9.1 Overview 9.9.2 Configuration ATmega128RFA1 96 The status of the security processing is indicated by register AES_STATUS. After a AES processing time of 24 µs the register bit AES_DONE changes to 1 (register AES_STATUS) indicating that the security operation has finished (see Timing Characteristics" ...

Page 97

... The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. ATmega128RFA1 Table 9-26 below. The column R/W R/ ...

Page 98

... Abbreviations ATmega128RFA1 98 To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer. For details refer to Table 9-27 Table 9-27. Frame Buffer Content for various Continuous Transmission Modulation Schemes Step Action Frame Content 11 Frame Buffer Random Sequence Write Access ...

Page 99

... PHY service data unit PSD - Power spectral mask QFN - Quad flat no-lead package RF - Radio frequency RSSI - Received signal strength indicator RX - Receiver SFD - Start-of-frame delimiter SHR - Synchronization header SPI - Serial peripheral interface SRAM - Static random access memory SSBF - Single side band filter TX - Transmitter ATmega128RFA1 99 ...

Page 100

... ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM). [5] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 [6] ATmega128RFA1 Software Programming Model Bit ($13C) AES_REQUEST Res ...

Page 101

... Bit 6:1 – Res5:0 - Reserved These bits are reserved for future use. • Bit 0 – AES_DONE - AES Operation Finished with Success This register bit indicates a successfully finished operation of the AES module. ATmega128RFA1 Value Description 0 AES Mode is ECB (Electronic Code Book). ...

Page 102

... AES_STATE – AES Plain and Cipher Text Buffer Register 9.12.4 AES_KEY – AES Encryption and Decryption Key Buffer Register 9.12.5 TRX_STATUS – Transceiver Status Register ATmega128RFA1 102 Bit ($13E) Read/Write Initial Value The AES_STATE register accesses a 16 byte internal data buffer. The buffer is accessed by reading or writing 16 times to the same address location (AES_STATE) ...

Page 103

... The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate a further state STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table are reserved. Table 9-33 TRX_STATUS Register Bits Register Bits TRX_STATUS4:0 ATmega128RFA1 Value Description 0 CCA calculation not finished 1 CCA calculation finished Value Description 0 Channel indicated as busy ...

Page 104

... TRX_STATE – Transceiver State Control Register ATmega128RFA1 104 Register Bits Bit 7 NA ($142) TRAC_STATUS2 TRAC_STATUS1 TRAC_STATUS0 Read/Write R Initial Value 0 Bit 3 NA ($142) TRX_CMD3 TRX_CMD2 Read/Write RW RW Initial Value 0 The states of the radio transceiver are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction ...

Page 105

... NA ($144) Res3 Res2 Read/Write R Initial Value 0 The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. • Bit 7 – PA_EXT_EN - External PA support enable ATmega128RFA1 while the radio transceiver state (see TRX_STATUS for the SLEEP ...

Page 106

... PHY_TX_PWR – Transceiver Transmit Power Control Register ATmega128RFA1 106 This register bit enables pin DIG3 and pin DIG4 to indicate the transmit state of the radio transceiver. The control of the external RF front-end is disabled when this bit is 0. Both pins DIG3 and DIG4 are then low. The control of the external front-end is enabled when this bit is 1 ...

Page 107

... RSSI value. • Bit 7 – RX_CRC_VALID - Received Frame CRC Status Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing a TRX24_RX_END interrupt and remains ATmega128RFA1 Value Description 0 2 µ ...

Page 108

... PHY_ED_LEVEL – Transceiver Energy Detection Level Register ATmega128RFA1 108 valid until the next TRX24_RX_END interrupt is issued, caused by a new frame reception. Table 9-39 RX_CRC_VALID Register Bits Register Bits RX_CRC_VALID • Bit 6:5 – RND_VALUE1:0 - Random Value reading register bits RND_VALUE. The value can be used for random numbers for security applications. Note that the radio transceiver shall be in Basic Operating Mode receive state. The values are updated every 1 µ ...

Page 109

... Table 9-42 CCA_MODE Register Bits Register Bits CCA_MODE1:0 • Bit 4:0 – CHANNEL4:0 - RX/TX Channel Selection These register bits define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. ATmega128RFA1 Value Description 0x00 Minimum result of last ED measurement 0x01 P(RF) = RSSI_BASE_VAL+ED [dBm] 0x02 ...

Page 110

... CCA_THRES – Transceiver CCA Threshold Setting Register ATmega128RFA1 110 Table 9-43 CHANNEL Register Bits Register Bits CHANNEL4:0 Bit 7 NA ($149) CCA_CS_THRES3 Read/Write RW Initial Value 1 Bit 5 NA ($149) CCA_CS_THRES1 Read/Write RW Initial Value 0 Bit 3 NA ($149) CCA_ED_THRES3 Read/Write RW Initial Value 0 Bit 1 NA ($149) ...

Page 111

... For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled a RX_START interrupt is issued only if the received SFD matches the register content of SFD_VALUE and a valid PHR is received. ATmega128RFA1 Resx5 ...

Page 112

... TRX_CTRL_2 – Transceiver Control Register 2 9.12.17 ANT_DIV – Antenna Diversity Control Register ATmega128RFA1 112 Table 9-45 SFD_VALUE Register Bits Register Bits SFD_VALUE7:0 Bit 7 NA ($14C) RX_SAFE_MODE Res4 Read/Write RW Initial Value 0 Bit ($14C) Res1 Res0 Read/Write R R Initial Value 0 0 This register controls the data rate setting of the radio transceiver. ...

Page 113

... These bits provide a static control of an Antenna Diversity switch. This register setting defines the selected antenna if ANT_DIV_EN is set to 0 (Antenna Diversity disabled). Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1. Table 9-50 ANT_CTRL Register Bits Register Bits ANT_CTRL1:0 ATmega128RFA1 Value Description 0 Antenna 0 1 ...

Page 114

... IRQ_MASK – Transceiver Interrupt Enable Register 9.12.19 IRQ_STATUS – Transceiver Interrupt Status Register ATmega128RFA1 114 Register Bits Bit ($14E) AWAKE_EN TX_END_EN Read/Write RW RW Initial Value 0 0 Bit 3 NA ($14E) RX_END_EN RX_START_EN Read/Write RW RW Initial Value 0 This register is used to enable or disable individual interrupts of the radio transceiver. ...

Page 115

... Table 9-52 AVDD_OK Register Bits Register Bits AVDD_OK • Bit 5:3 – Resx5:3 - Reserved • Bit 2 – DVDD_OK - DVDD Supply Voltage Valid This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high if DVREG_EXT = 1. ATmega128RFA1 Resx5 Resx4 R ...

Page 116

... BATMON – Battery Monitor Control and Status Register ATmega128RFA1 116 Table 9-53 DVDD_OK Register Bits Register Bits DVDD_OK • Bit 1:0 – DVREG_TRIM1:0 - Reserved Table 9-54 DVREG_TRIM Register Bits Register Bits DVREG_TRIM1:0 Bit 7 NA ($151) BAT_LOW BAT_LOW_EN Read/Write RW RW Initial Value ...

Page 117

... Table 9-57 BATMON_VTH Register Bits Register Bits BATMON_VTH3:0 Bit 7 NA ($152) XTAL_MODE3 XTAL_MODE2 Read/Write RW RW Initial Value 1 ATmega128RFA1 Value Description 0 Enables the low range, see BATMON_VTH 1 Enables the high range, see BATMON_VTH Value Description 0x0 2.550V (BATMON_HR=1) 1.70V (BATMON_HR=0) 0x1 2.625V (BATMON_HR=1) 1.75V ...

Page 118

... RX_SYN – Transceiver Receiver Sensitivity Control Register ATmega128RFA1 118 Bit 3 NA ($152) XTAL_TRIM3 XTAL_TRIM2 Read/Write RW RW Initial Value 0 This register controls the operation of the 16MHz crystal oscillator. • Bit 7:4 – XTAL_MODE3:0 - Crystal Oscillator Operating Mode These register bits set the operating mode of the 16 MHz crystal oscillator. For normal operation the default value is set to XTAL_MODE = 0xF after reset ...

Page 119

... Bit 5 – AACK_FLTR_RES_FT - Filter Reserved Frames This register bit shall only AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as ATmega128RFA1 Value Description 0x0 RX_THRES RSSI_BASE_VAL (Reset value); RSSI value not considered 0x1 RX_THRES > ...

Page 120

... FTN_CTRL – Transceiver Filter Tuning Control Register ATmega128RFA1 120 specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4 section 7.2.1.1.1. If AACK_FLTR_RES_FT = 0 a received, reserved frame is only checked for a valid FCS. • Bit 4 – AACK_UPLD_RES_FT - Process Reserved Frames If AACK_UPLD_RES_FT = 1 received frames indicated as reserved are further processed ...

Page 121

... PLL_CF_START = 1 initiates the center frequency calibration. The calibration cycle has finished after 35 µs (typical). The register bit is cleared immediately after finishing the calibration. • Bit 6:0 – Resx6:0 - Reserved Bit 7 NA ($15B) PLL_DCU_START Resx6 Read/Write RW Initial Value 0 ATmega128RFA1 Resx1 Resx0 Resx6 ...

Page 122

... These bits decode the version number of the device according to the following table. Table 9-63 VERSION_NUM Register Bits Register Bits VERSION_NUM7 Resx1 Resx0 PART_NUM7 Value Description 0x83 ATmega128RFA1 part number Value Description 2 Revision AB 3 Revision C 4 Revision D PLL_DCU PART_NUM VERSION_NUM 8266A-MCU Wireless-12/09 ...

Page 123

... NA ($160) SHORT_ADDR_07:00 Read/Write Initial Value This register contains the lower 8 bits of the MAC short address for Frame Filter address recognition. • Bit 7:0 – SHORT_ADDR_07:00 - MAC Short Address These bits contain the bits [7:0] of the MAC short address. ATmega128RFA1 MAN_ID_07: ...

Page 124

... SHORT_ADDR_1 – Transceiver MAC Short Address Register (High Byte) 9.12.34 PAN_ID_0 – Transceiver Personal Area Network ID Register (Low Byte) 9.12.35 PAN_ID_1 – Transceiver Personal Area Network ID Register (High Byte) 9.12.36 IEEE_ADDR_0 – Transceiver MAC IEEE Address Register 0 ATmega128RFA1 124 Bit 7 ...

Page 125

... NA ($167) Read/Write Initial Value This register contains the bits [31:24] of the MAC IEEE address for Frame Filter address recognition. • Bit 7:0 – IEEE_ADDR_37:30 - MAC IEEE Address These bits map to the bits [31:24] of the 64 bit MAC IEEE address. ATmega128RFA1 IEEE_ADDR_17: ...

Page 126

... IEEE_ADDR_4 – Transceiver MAC IEEE Address Register 4 9.12.41 IEEE_ADDR_5 – Transceiver MAC IEEE Address Register 5 9.12.42 IEEE_ADDR_6 – Transceiver MAC IEEE Address Register 6 9.12.43 IEEE_ADDR_7 – Transceiver MAC IEEE Address Register 7 ATmega128RFA1 126 Bit ($168) Read/Write Initial Value This register contains the bits [39:32] of the MAC IEEE address for Frame Filter address recognition. • ...

Page 127

... MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets canceled. According to IEEE 802.15.4 the valid range of MAX_CSMA_RETRIES value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. This may especially be required for slotted acknowledgment operation. MAX_CSMA_RETRIES = 6 is reserved. ATmega128RFA1 6 MAX_FRAME_RETRIES2 ...

Page 128

... CSMA_SEED_0 – Transceiver CSMA-CA Random Number Generator Seed Register ATmega128RFA1 128 Table 9-67 MAX_CSMA_RETRIES Register Bits Register Bits MAX_CSMA_RETRIES2:0 • Bit 0 – SLOTTED_OPERATION - Set Slotted Acknowledgment When using RX_AACK mode in networks operating in beacon or slotted mode according to IEEE 802.15.4-2006, SLOTTED_OPERATION indicates that acknowledgment frames are to be sent on back- off slot boundaries (slotted acknowledgment) ...

Page 129

... This is done in the assumption that a future version of the IEEE 802.15.4 standard might change the length or structure of the auxiliary security header, so that it is not possible to safely detect whether the MAC command frame is actually a data request command or not. ATmega128RFA1 6 AACK_FVN_MODE0 RW ...

Page 130

... CSMA_BE – Transceiver CSMA-CA Back-off Exponent Control Register ATmega128RFA1 130 • Bit 4 – AACK_DIS_ACK - Disable Acknowledgment Frame Transmission If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode even if requested. • Bit 3 – AACK_I_AM_COORD - Set Personal Area Network Coordinator This register bit has to be set if the node is a PAN coordinator ...

Page 131

... Table 9-72 TST_CTRL_DIG Register Bits Register Bits TST_CTRL_DIG3:0 Bit 7 NA ($17B) RX_LENGTH7 RX_LENGTH6 Read/Write RW RW Initial Value 0 ATmega128RFA1 Value Description 0 Minimum value of minimum back-off exponent. 1 ... 8 Maximum value of minimum back-off exponent. MIN_BE must be smaller or equal to MAX_BE. 6 Resx6 ...

Page 132

... TRXFBST – Start of frame buffer 9.12.51 TRXFBEND – End of frame buffer ATmega128RFA1 132 Bit 3 NA ($17B) RX_LENGTH3 RX_LENGTH2 Read/Write RW RW Initial Value 0 This register contains the frame length information of a received frame. This information is not stored in the frame buffer. The frame length information is written to this register after the last received octet. • ...

Page 133

... Write Access: 1. Write the upper 3 byte 2. Writing the LL-Byte stores the 32 bit value in the counter registers The same temporary register is used for all 32 bit register of the MAX symbol counter. ATmega128RFA1 "SCCR0 – Symbol . The bit SCCKSEL can not be written if the 133 ...

Page 134

... Transceiver Personal Area Network ID Register (Low Beacon timestamps can also be generated manually. Writing “1” to SCMBTS of Register SCCR0 captures the current symbol counter value and stores it in the beacon timestamp register. The bit is cleared automatically afterwards. "Interrupt Vectors in ATmega128RFA1" "PAN_ID_0 – Byte)" on page 124 ...

Page 135

... SFD value has been received completely. For an incoming frame, the register is valid after the RX_START IRQ was issued until the next RX_START IRQ. SFD timestamps are generated for all incoming frames with valid SFD and length field even if the PSDU is corrupted (invalid FCS). ATmega128RFA1 135 ...

Page 136

... Relative Compare Mode for Superframe Access Timing ATmega128RFA1 136 Figure 10-1. SFD and Beacon Timestamp Generation Note that Figure 10-1 contains no exact timing information for visualization only. The beacon timestamp register is updated with the SFD timestamp value at the end of the frame (RX_END IRQ), if the received frame was a beacon frame with valid FCS and expected source PAN identifier or { PAN_ID_1, PAN_ID_0} = 0xFFFF ...

Page 137

... After the frame operations are finished, the system can go back to sleep until the next compare match event occurs. Bit ($E4) Read/Write Initial Value This register contains the most significant byte of the 32 bit Symbol Counter. • Bit 7:0 – SCCNTHH7:0 - Symbol Counter Register HH-Byte ATmega128RFA1 SCCNTHH7 ...

Page 138

... SCCNTHL – Symbol Counter Register HL-Byte 10.11.3 SCCNTLH – Symbol Counter Register LH-Byte 10.11.4 SCCNTLL – Symbol Counter Register LL-Byte 10.11.5 SCTSRHH – Symbol Counter Frame Timestamp Register HH-Byte ATmega128RFA1 138 Bit ($E3) Read/Write Initial Value This register contains the second most significant byte of the 32 bit Symbol Counter. ...

Page 139

... Register. The Beacon Timestamp Register is updated with the contents of the Frame Timestamp Register if the received frame was a valid beacon frame with matching source PAN identifier or register {PAN_ID_1, PAN_ID_0} = 0xFFFF. • Bit 7:0 – SCBTSRHH7:0 - Symbol Counter Beacon Timestamp Register HH- Byte ATmega128RFA1 ...

Page 140

... SCBTSRHL – Symbol Counter Beacon Timestamp Register HL-Byte 10.11.11 SCBTSRLH – Symbol Counter Beacon Timestamp Register LH-Byte 10.11.12 SCBTSRLL – Symbol Counter Beacon Timestamp Register LL-Byte 10.11.13 SCOCR1HH – Symbol Counter Output Compare Register 1 HH-Byte ATmega128RFA1 140 Bit ($E7) Read/Write RW RW ...

Page 141

... Bit 7:0 – SCOCR1LL7:0 - Symbol Counter Output Compare Register 1 LL-Byte Bit ($F4) Read/Write Initial Value This register contains the most significant byte of the 32 bit compare value for the second compare unit • Bit 7:0 – SCOCR2HH7:0 - Symbol Counter Output Compare Register 2 HH-Byte ATmega128RFA1 SCOCR1HL7 ...

Page 142

... SCOCR2HL – Symbol Counter Output Compare Register 2 HL-Byte 10.11.19 SCOCR2LH – Symbol Counter Output Compare Register 2 LH-Byte 10.11.20 SCOCR2LL – Symbol Counter Output Compare Register 2 LL-Byte 10.11.21 SCOCR3HH – Symbol Counter Output Compare Register 3 HH-Byte ATmega128RFA1 142 Bit ($F3) Read/Write RW RW ...

Page 143

... Bit 7 – SCRES - Symbol Counter Synchronization If this bit is set to 1, the 16 MHz clock prescaler as well as the backoff slot counter is cleared. This function can be used to align the symbol timing within one 16 µs symbol period and to restart the backoff slot counter with a complete 320 µs period. This ATmega128RFA1 ...

Page 144

... SCCR1 – Symbol Counter Control Register 1 ATmega128RFA1 144 feature works only if the symbol counter module operates with the 16 MHz clock from XTAL1. After switching to RTC clock source, the symbol period synchronization is lost. This bit is cleared automatically. • Bit 6 – SCMBTS - Manual Beacon Timestamp With this bit a manual beacon timestamp can be generated ...

Page 145

... Bit 4 – IRQSBO - Backoff Slot Counter IRQ This interrupt is generated every 320 µs, that means every 20 symbols. • Bit 3 – IRQSOF - Symbol Counter Overflow IRQ This interrupt is generated when the 32 bit counter turns from 0xFFFFFFF to 0x00000000. • Bit 2 – IRQSCP3 - Compare Unit 3 Compare Match IRQ ATmega128RFA1 Res3 ...

Page 146

... SCIRQM – Symbol Counter Interrupt Mask Register ATmega128RFA1 146 This interrupt indicates a compare match on compare unit 3. • Bit 1 – IRQSCP2 - Compare Unit 2 Compare Match IRQ This interrupt indicates a compare match on compare unit 2. • Bit 0 – IRQSCP1 - Compare Unit 1 Compare Match IRQ This interrupt indicates a compare match on compare unit 1 ...

Page 147

... Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. ATmega128RFA1 "Power Management and Sleep Modes" Flash and ...

Page 148

... ADC Clock – clkADC 11.3 Clock Sources 11.3.1 Default Clock Source 11.3.2 Clock Start-up Sequence ATmega128RFA1 148 The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted ...

Page 149

... By changing the OSCCAL register (see page 153) from Software possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in section "Clock Characteristics" on page ATmega128RFA1 510. and "Internal Oscillator "System Clock Prescaler" on "OSCCAL – Oscillator Calibration Value" on 502. " ...

Page 150

... Internal Oscillator 11.6 External Clock ATmega128RFA1 150 When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre- programmed calibration value, see the section Table 11-3 ...

Page 151

... AVR core clock, it remains enabled even if the radio transceiver is in SLEEP mode or its power reduction bit PRTRX24 is set. Table 11-9. Transceiver Crystal Clock Operating Mode Frequency Range (MHz) 16 Notes: 1. All CKSEL fuse values have the same significance. ATmega128RFA1 CKSEL3:0 0000 Additional Delay from Reset 4.0 ms ...

Page 152

... See section crystal connection. The ATmega128RFA1 has a system clock prescaler, and the system clock can be divided by setting the “CLKPR – Clock Prescale Register”. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low ...

Page 153

... Interrupts must be disabled when changing prescaler settings to make sure the write procedure is not interrupted not required to change the prescaler setting of an existing software package written for an 8MHz internal RC oscillator. The change of the prescaler (additional 1:2 divider) is compensated by doubling the RC oscillator frequency of the ATmega128RFA1. Bit 7 6 ...

Page 154

... CLKPR – Clock Prescale Register ATmega128RFA1 154 Register Bits Bit ($61) CLKPCE Res2 Res1 Read/Write Initial Value • Bit 7 – CLKPCE - Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero ...

Page 155

... Wireless-12/09 Register Bits ATmega128RFA1 Value Description 0xB Reserved 0xC Reserved 0xD Reserved 0xE Reserved 0xF Division factor 1 only permitted for RC- Oscillator. Flash and EEPROM programming is not allowed. 155 ...

Page 156

... Deep-sleep mode to avoid an undefined ADC operation. In chapter "System Clock and Clock Options" on page 147 in the ATmega128RFA1, and their distribution were presented. 147 is helpful in selecting an appropriate sleep mode. The following table shows the different sleep modes and their wake-up sources. ...

Page 157

... This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, ATmega128RFA1 Wake-up Sources ...

Page 158

... Power-down Mode 12.2.4 Power-save Mode 12.2.5 Standby Mode 12.2.6 Extended Standby Mode ATmega128RFA1 158 an external level interrupt on INT7 pin change interrupt can wakeup the MCU from ADC Noise Reduction mode. When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode ...

Page 159

... When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be ATmega128RFA1 "PRR0 – Power Reduction Register0" on 168, provide a method to stop the clock to individual " ...

Page 160

... Watchdog Timer 12.4.6 Port Pins 12.4.7 On-chip Debug System 12.4.8 Symbol Counter 12.4.9 Radio Transceiver ATmega128RFA1 160 used immediately. Refer to "Internal Voltage Reference" on page 179 start-up time. If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power ...

Page 161

... The blocks will be enabled in the following order: 1. Bandgap reference and voltage regulator, 2. Digital voltage regulator (DVREG) and low leakage voltage regulator (LLVREG), 3. SRAM block #0 (lower 4k bytes), 4. SRAM block #1, 5. SRAM block #2, ATmega128RFA1 "Power-chain" below . 163. drt_sw itch pow er_ sw itch R adio ...

Page 162

... bandgap startup S LEE P bandgap ATmega128RFA1 162 6. SRAM block #3 (upper 4k bytes), 7. Radio transceiver including AES engine, 8. Non-volatile memory. If the power-chain is completely enabled the standard AVR wake-up procedure continues. Figure 12-2 shows the chained startup procedure after power up. A module is only switched not deselected by power reduction register (PRR1 or PRR2). This is possible for SRAM blocks and radio transceiver power switch ...

Page 163

... DRT voltage settings are preprogrammed during the manufacturing process and need not to be changed. The main features of the Voltage Regulator blocks are: • Bandgap stabilized 1.8V supply for analog and digital domain; ATmega128RFA1 Powerchain (7) off 168). This enables the application ...

Page 164

... Low dropout (LDO) voltage regulator; • Configurable to use an external voltage regulator; The internal voltage regulators supply a stabilized voltage to the ATmega128RFA1. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. The DVREG is enabled during startup and is switched off if the power-chain is disabled ...

Page 165

... The registers are implemented in the I/O clock domain while the logic of the Low Leakage Voltage Regulator runs with 64 kHz (clock output of the 128 kHz RC oscillator divided by 2). It takes at least two 64 kHz clock cycles before the data written to the ATmega128RFA1 "Low Leakage Voltage is not fixed. It depends on the ...

Page 166

... Register Description 12.6.1 SMCR – Sleep Mode Control Register ATmega128RFA1 166 register take effect in the regulator circuit. The write access from the software must be aware of this process. Furthermore the value of LLDRH must be written first followed by LLDRL. Otherwise the LLDRH write access will be ignored. The following Assembler code fragment shows a working example ...

Page 167

... Bit 0 – PRADC - Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled (reset ADEN bit in register ADCSRA) before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. ATmega128RFA1 ...

Page 168

... PRR1 – Power Reduction Register 1 12.6.4 PRR2 – Power Reduction Register 2 ATmega128RFA1 168 Bit ($65) Res PRTRX24 PRTIM5 Read/Write Initial Value • Bit 7 – Res - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. • ...

Page 169

... A reset forces the radio transceiver into the TRX_OFF state and resets all transceiver register to their default values. A reset is initiated with bit TRXRST = H. The bit is cleared automatically During transceiver reset the microcontroller has to set the radio transceiver control bit SLPTR to the default value. ATmega128RFA1 ...

Page 170

... DRTRAM0 – Data Retention Configuration Register of SRAM 0 12.6.7 DRTRAM1 – Data Retention Configuration Register of SRAM 1 ATmega128RFA1 170 Bit ($135) Res1 Res0 DRTSWOK ENDRT Read/Write Initial Value The DRTRAM0 register controls the behavior of SRAM block 0 in the power-states "power-save" and "power-down". To prevent any data loss the SRAM will not completely disconnected from the power supply ...

Page 171

... During "Deep-Sleep" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used. Otherwise the SRAM is switched off (disconnected from the power supply) and all its data are lost. • Bit 3:0 – Resx3:0 - Reserved ATmega128RFA1 ...

Page 172

... LLCR – Low Leakage Voltage Regulator Control Register ATmega128RFA1 172 Bit ($12F) Res1 Res0 LLDONE LLCOMP Read/Write Initial Value This register allows to monitor and to control the calibration process of the low-leakage voltage regulator. The automatic calibration is the normal operation mode. However, certain circumstances may require to disable this automatic process for instance to save power-up time ...

Page 173

... Bit 7:4 – Res3:0 - Reserved These bits are reserved for future use. • Bit 3:0 – LLDRL3:0 - Low-Byte Data Register Bits Value of the low-byte calibration result Table 12-6 LLDRL Register Bits Register Bits LLDRL3:0 ATmega128RFA1 LLDRH4 LLDRH3 LLDRH2 LLDRH1 LLDRH0 RW ...

Page 174

... DPDS0 – Port Driver Strength Register 0 ATmega128RFA1 174 Bit ($136) PFDRV1 PFDRV0 PEDRV1 PEDRV0 PDDRV1 PDDRV0 PBDRV1 PBDRV0 Read/Write Initial Value The output driver strength can be set individually for each digital I/O port. The following tables show output current levels for a typical supply voltage of DEVDD = 3.3V. Refer to section " ...

Page 175

... Bit 1:0 – PGDRV1:0 - Driver Strength Port G Driver strength can be set for port G except the port pins PG3 and PG4. The leakage current of the ports PG3 and PG4 is reduced. Table 12-11 PGDRV Register Bits Register Bits PGDRV1:0 ATmega128RFA1 Res2 Res1 ...

Page 176

... The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in Sources" on page 148. The ATmega128RFA1 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). ...

Page 177

... DEVDD decreases below the detection level. Figure 13-2. MCU Start-up, RSTN Tied to DEVDD V POT DEVDD V RST RSTN t TOUT TIME-OUT INTERNAL RESET ATmega128RFA1 DATA BUS MCU Status Register (MCUSR Delay Counters CK TIMEOUT 502. The POR circuit can be used to Q 177 ...

Page 178

... TIME-OUT INTERNAL RESET ATmega128RFA1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the EVDD level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should ...

Page 179

... TOUT TIME-OUT INTERNAL RESET ATmega128RFA1 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. ...

Page 180

... WDE WDIF WDIE ATmega128RFA1 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR -Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...

Page 181

... C Code Example void WDT_off(void) { disable_interrupt(); watchdog_reset(); /* Clear WDRF in MCUSR*/ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); } ATmega128RFA1 181 ...

Page 182

... ATmega128RFA1 182 Note: 1. The example code assumes that the part specific header file is included. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets ...

Page 183

... This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. ATmega128RFA1 ...

Page 184

... ATmega128RFA1 184 • Bit 6 – WDIE - Watchdog Timeout Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs ...

Page 185

... Wireless-12/09 Register Bits ATmega128RFA1 Value Description 0x04 Oscillator Cycles 32k, (0.25s) 0x05 Oscillator Cycles 64k, (0.5s) 0x06 Oscillator Cycles 128k, (1.0s) 0x07 Oscillator Cycles 256k, (2.0s) 0x08 Oscillator Cycles 512k, (4.0s) 0x09 Oscillator Cycles 1024k, (8.0s) 185 ...

Page 186

... Introduction ATmega128RFA1 186 All ATmega128RFA1 ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input) ...

Page 187

... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATmega128RFA1 Figure 14-2 below 187 ...

Page 188

... Toggling the Pin 14.2.4 Switching Between Input and Output 14.2.5 Reading the Pin Value ATmega128RFA1 188 Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. ...

Page 189

... The resulting pin values are read back again, but as previously discussed, a NOP instruction is included to be able to read back the value recently assigned to some of the pins. ATmega128RFA1 and PD,MAX ...

Page 190

... Digital Input Enable and Sleep Modes 14.2.7 Unconnected Pins ATmega128RFA1 190 (1) Assembly Code Example … ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) ...

Page 191

... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 14-5. Alternate Port Functions ATmega128RFA1 (1) Figure 191 ...

Page 192

... Alternate Functions of Port B ATmega128RFA1 192 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk , SLEEP, and PUD are common to all ports. All other signals are unique for I/O each pin. The following table summarizes the function of the overriding signals. The pin and port ...

Page 193

... OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. ATmega128RFA1 193 ...

Page 194

... ATmega128RFA1 194 PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source. • MISO/PDO/PCINT3 – Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3 ...

Page 195

... INT2/RXD 1(External Interrupt2 Input or USART1 Receive Pin) PD1 INT1/SDA (External Interrupt1 Input or TWI Serial Data) PD0 INT0/SCL (External Interrupt0 Input or TWI Serial Clock) The alternate pin configuration is as follows: • T0 – Port D, Bit 7 T0, this is Timer/Counter0 counter source. ATmega128RFA1 PB5/OC1A PB4/OC2A ...

Page 196

... ATmega128RFA1 196 • T1 – Port D, Bit 6 T1, this is Timer/Counter1 counter source. • XCK1 – Port D, Bit 5 XCK1, USART1 External clock: The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode. ...

Page 197

... INT4/OC3B (External Interrupt4 Input or Output Compare and PWM Output B for Timer/Counter3) PE3 AIN1/OC3A (Analog Comparator Negative Input or Output Compare and PWM Output A for Timer/Counter3) PE2 AIN0/XCK0 (Analog Comparator or Positive Input or USART0 external clock input/output) PE1 TXD0 (USART0 Transmit Pin) ATmega128RFA1 PD5/XCK1 PD4/ICP1 1 0 XCK1 OUTPUT 0 ENABLE XCK1 OUTPUT ...

Page 198

... ATmega128RFA1 198 Port Alternate Function Pin PE0 RXD0/PCINT8 (USART0 Receive Pin or Pin Change Interrupt8) • INT7/ICP3/CLKO – Port E, Bit 7 INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. ICP3, Input Capture Pin 3: The PE7 pin can act as an input capture pin for Timer/Counter3 ...

Page 199

... This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. ATmega128RFA1 relates the alternate functions of Port E to 191. PE5/INT5/OC3C ...

Page 200

... ATmega128RFA1 200 Table 14-12. Port F Pins Alternate Functions Port Pin Alternate Function PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) PF5 ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select) ...

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