ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 309

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21 8-bit Timer/Counter2 with PWM and Asynchronous Operation
21.1 Features
21.2 Overview
21.2.1 Registers
21.2.2 Definitions
8266A-MCU Wireless-12/09
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The
main features are:
• Single channel counter
• Clear timer on compare match (auto reload)
• Glitch-free, phase-correct pulse-width modulator (PWM)
• Frequency generator
• 10 bit clock prescaler
• Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B)
• Able to run with external 32 kHz watch crystal independent of the I/O clock
A simplified block diagram of the 8-bit Timer/Counter is shown on
310. For the current placement of I/O pins, see chapter
CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the
page
The Power Reduction Timer/Counter2 bit PRTIM2 in register PRR0 (see
Power Reduction Register0" on page
Timer/Counter2 module.
Note: OC2B is implemented but not routed to a pin and for this reason it can’t be used.
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8
bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the
Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the
Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, asynchronously clocked
from the TOSC1/2 pins or alternatively from the Automated Meter Reading (AMR) pin
as detailed later in this section. The asynchronous operation is controlled by the
Asynchronous Status Register (ASSR). The Clock Select logic block controls which
clock source the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the Clock
Select logic is referred to as the timer clock (clk
The double buffered Output Compare Register (OCR2A and OCR2B) are compared
with the Timer/Counter value at all times. The result of the compare can be used by the
Waveform Generator to generate a PWM or variable frequency output on the Output
Compare pins (OC2A and OC2B). See chapter
details. The compare match event will also set the Compare Flag (OCF2A or OCF2B)
which can be used to generate an Output Compare interrupt request.
Many register and bit references in this document are written in general form. A lower
case “n” replaces the Timer/Counter number, in this case 2. However, when using the
323.
167) must be written to zero to enable
T2
"Output Compare Unit" on page 316
).
ATmega128RFA1
"Pin Configurations" on page
"Register Description" on
Figure 21-1 on
"PRR0 –
page
309
for
2.