ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 111

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.14 RX_CTRL – Transceiver Receive Control Register
9.12.15 SFD_VALUE – Start of Frame Delimiter Value Register
8266A-MCU Wireless-12/09
These bits define the received power threshold of the Energy above threshold
algorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES
[dBm]. Any received power above this level is interpreted as a busy channel.
The register controls the sensitivity of the Antenna Diversity Mode. Note that in High
Data Rate modes the ACR module will always be disabled.
• Bit 7:4 – Resx7:4 - Reserved
• Bit 3:0 – PDT_THRES3:0 - Receiver Sensitivity Control
These register bits control the sensitivity of the receiver correlation unit. If the Antenna
Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it
shall be set back to the reset value. Values not listed in the following table are reserved.
Table 9-44 PDT_THRES Register Bits
This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a
received frame. The lower 4 bits must not be all zero to avoid decoding conflicts.
• Bit 7:0 – SFD_VALUE7:0 - Start of Frame Delimiter Value
For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default
value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value
can be changed to any other value. If enabled a RX_START interrupt is issued only if
the received SFD matches the register content of SFD_VALUE and a valid PHR is
received.
Bit
NA ($14A)
Read/Write
Initial Value
Bit
NA ($14A)
Read/Write
Initial Value
Bit
NA ($14B)
Read/Write
Initial Value
Register Bits
PDT_THRES3:0
PDT_THRES3
RW
7
1
Resx7
RW
RW
7
1
3
0
RW
6
0
RW
PDT_THRES2
5
1
Resx6
RW
RW
6
0
2
1
SFD_VALUE7:0
Value
RW
0x7
0x3
4
0
RW
PDT_THRES1
3
0
Resx5
Description
Reset value, to be used if Antenna Diversity
algorithm is disabled
Recommended correlator threshold for
Antenna Diversity operation
RW
RW
5
1
1
1
RW
2
1
ATmega128RFA1
RW
PDT_THRES0
1
1
Resx4
RW
RW
4
1
0
1
RW
0
1
SFD_VALUE
RX_CTRL
RX_CTRL
111