ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 401

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.9 Register Description
25.9.1 TWBR – TWI Bit Rate Register
8266A-MCU Wireless-12/09
• Two or more masters are accessing different slaves. In this case, arbitration will
This is summarized in
Figure 25-21. Possible Status Codes Caused by Arbitration
The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the
Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on
Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at
least 16 times higher than the SCL frequency.
• Bit 7:0 – TWBR7:0 - TWI Bit Rate Register Value
The TWBR register selects the division factor for the bit rate generator. The bit rate
generator is a frequency divider which generates the SCL clock frequency in the Master
modes. See section "Bit Rate Generator Unit" for calculating bit rates.
Bit
NA ($B8)
Read/Write
Initial Value
START
will lose the arbitration. Losing masters will switch to not addressed Slave mode or
wait until the bus is free and transmit a new START condition, depending on
application software action.
occur in the SLA bits. Masters trying to output a one on SDA while another Master
outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to
Slave mode to check if they are being addressed by the winning Master. If
addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed
Slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
Address / General Call
RW
7
0
Direction
received
Own
Yes
Arbitration lost in SLA
RW
6
0
SLA
Figure 25-21
Read
Write
RW
5
0
No
RW
below. Possible status values are given in circles.
4
0
TWBR7:0
68/78
38
B0
RW
3
0
Arbitration lost in Data
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
RW
2
0
ATmega128RFA1
Data
RW
1
0
RW
0
0
TWBR
STOP
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