ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 275
ATMEGA128RFA1-ZU
Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
4.ATMEGA128RFA1-ZU.pdf
(524 pages)
Specifications of ATMEGA128RFA1-ZU
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
- ATMEGA128-16AU PDF datasheet
- ATAVR128RFA1-EK1 PDF datasheet #2
- ATAVR128RFA1-EK1 PDF datasheet #3
- ATMEGA128RFA1-ZU PDF datasheet #4
- Current page: 275 of 524
- Download datasheet (5Mb)
18.11.15 TIFR1 – Timer/Counter1 Interrupt Flag Register
8266A-MCU Wireless-12/09
The corresponding Interrupt Vector is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1 - Timer/Counter1 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV1 Flag, located in TIFR1, is set.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 5 – ICF1 - Timer/Counter1 Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is
set when the counter reaches the TOP value. ICF1 is automatically cleared when the
Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing
a logic one to its bit location.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 3 – OCF1C - Timer/Counter1 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register C (OCR1C). Note that a Forced Output Compare (FOC1C)
strobe will not set the OCF1C Flag. OCF1C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF1C can be cleared by
writing a logic one to its bit location.
• Bit 2 – OCF1B - Timer/Counter1 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B)
strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by
writing a logic one to its bit location.
• Bit 1 – OCF1A - Timer/Counter1 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A)
strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by
writing a logic one to its bit location.
• Bit 0 – TOV1 - Timer/Counter1 Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting of the Timer/Counter1
Control Register. In Normal and CTC modes, the TOV1 Flag is set when the timer
Bit
$16 ($36)
Read/Write
Initial Value
Res1
R
7
0
Res0
R
6
0
ICF1
RW
5
0
Res
R
4
0
OCF1C
RW
3
0
ATmega128RFA1
OCF1B
RW
2
0
OCF1A
RW
1
0
TOV1
RW
0
0
TIFR1
275
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