ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 15

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7 Instruction Execution Timing
7.8 Reset and Interrupt Handling
8266A-MCU Wireless-12/09
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
Figure 7-5 below
clock cycle an ALU operation using two register operands is executed, and the result is
stored back to the destination register.
Figure 7-5. Single Cycle ALU operation
Register Operands Fetch
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically
disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section
The lowest addresses in the program memory space are by default defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in
page
lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to
the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). Refer to
can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
211. The list also determines the priority levels of the different interrupts. The
Result Write Back
clk
clk
CPU
shows the internal timing concept for the Register File. In a single
CPU
"Interrupts" on page 211
"Memory Programming" on page
T1
T1
"Memory Programming" on page 464
for more information. The Reset Vector
T2
T2
ATmega128RFA1
464.
T3
T3
for details.
"Interrupts" on
T4
T4
15