ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 427

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.11 Register Description
27.11.1 ADMUX – ADC Multiplexer Selection Register
8266A-MCU Wireless-12/09
The A/D conversion result will always be a positive number for both V
V
equation (see chapter
The conversion result is coded as described in
with a GAIN of 0.5. It is not possible to read both V
However the time required for the A/D conversion is short compared to the time
constant of a DRT voltage change.
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in the following table.
Changes of these bits will only take effect until the first conversion start is requested by
setting ADSC. After this the ADC has to be disabled and enabled again for new
reference selections. The internal voltage reference options may not be used if an
external reference voltage is being applied to the AREF pin.
Table 27-10. Reference Voltage Selections for ADC
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the A/D conversion result in the ADC Data
Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right
adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see
"ADCL and ADCH – The ADC Data Register" on page
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs is connected to the
ADC. See
conversion, the change will not go in effect until this conversion is complete (ADIF in
Bit
NA ($7C)
Read/Write
Initial Value
Parameter
ADC Clock
V
Start-up time
Tracking time
DRTBBN
REFS1
REF
0
0
1
1
. The SRAM supply voltage is easily calculated according to the following
Table 27-11 on page 428
REFS1
REFS0
RW
7
0
0
1
0
1
Register
ADCSRB
ADCSRA
ADMUX
ADCSRC
ADCSRC
REFS0
V
RW
"SRAM with Data Retention" on page
Reference Voltage Selection
AREF, Internal V
AVDD (1.8V)
Internal 1.5V Voltage Reference (no external capacitor at AREF pin)
Internal 1.6V Voltage Reference (no external capacitor at AREF pin)
6
0
DD
,
SRAM
ADLAR
Recommended Setup
MUX5 = 1;
Select a clock frequency of 500kHz or lower;
Select the internal 1.6V reference voltage;
Standard requirement of 20µs is sufficient;
Setting ADTHT = 0 is sufficient;
RW
,
5
0
DRT
=
for details. If these bits are changed during a
V
MUX4
REF
RW
DD
4
0
turned off
−
(
V
MUX3
RW
DRTBBP
3
0
"ADC Conversion Result" on
DRTBBP
ATmega128RFA1
+
MUX2
432.
RW
V
2
0
DRTBBN
and V
163):
MUX1
DRTBBN
RW
)
1
0
at the same time.
MUX0
RW
0
0
DRTBBP
page 423
ADMUX
and
427