ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 462

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.7 Register Description
30.7.1 SPMCSR – Store Program Memory Control Register
462
ATmega128RFA1
The Store Program Memory Control Register contains the control bits needed to control
the Boot Loader operations. Note: Only one SPM instruction should be active at any
time.
• Bit 7 – SPMIE - SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one),
the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as
long as the SPMEN bit in the SPMCR register is cleared.
• Bit 6 – RWWSB - Read While Write Section Busy
When a self-programming (page erase or page write) operation to the RWW section is
initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the
RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit
is written to one after a self-programming operation is completed. Alternatively the
RWWSB bit will automatically be cleared if a page load operation is initiated.
• Bit 5 – SIGRD - Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within
three clock cycles will read a byte from the signature row into the destination register. A
SPM instruction within four cycles after SIGRD and SPMEN are set, will have no effect.
This operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE - Read While Write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW section
is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW
section, the user software must wait until the programming is completed (SPMEN will
be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN,
the next SPM instruction within four clock cycles re-enables the RWW section. The
RWW section cannot be re-enabled while the Flash is busy with a page erase or a page
write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the
Flash load operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET - Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and
the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared
upon completion of the lock bit set, or if no SPM instruction is executed within four clock
cycles. A LPM instruction within three cycles after BLBSET and SPMEN are set in the
SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the
Z pointer) into the destination register.
• Bit 2 – PGWRT - Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles executes page write, with the data stored in the temporary buffer. The
page address is taken from the high part of the Z pointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM
Bit
$37 ($57)
Read/Write
Initial Value
SPMIE
RW
7
0
RWWSB
R
6
0
SIGRD
RW
5
0
RWWSRE BLBSET PGWRT
RW
4
0
RW
3
0
RW
2
0
PGERS
RW
1
0
8266A-MCU Wireless-12/09
SPMEN
RW
0
0
SPMCSR