ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 76

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6.2 Transmitter (TX)
9.6.2.1 Overview
Figure 9-21. Transmitter Block Diagram
9.6.2.2 Frame Transmit Procedure
9.6.2.3 Configuration
9.6.2.4 TX Power Ramping
R FP
D IG3/4
R FN
76
ATmega128RFA1
PA
Buf
The transmitter consists of a digital base band processor (TX BBP) and an analog front
end as shown in the following figure.
The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-
symbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in section 6.5.2.
The O-QPSK modulation signal is generated and fed into the analog radio front end.
The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to
the RF signal which is amplified by the power amplifier (PA). The PA output is internally
connected to bidirectional differential antenna pins (RFP, RFN) so that no external
antenna switch is needed.
The frame transmit procedure including writing PSDU data in the Frame Buffer and
initiating a transmission is described in section
84. The controller must ensure to provide valid frame data before starting the frame
transmission. For save operation, it is recommended to write the complete frame into
the Frame Buffer before starting the frame transmission.
The maximum output power of the transmitter is typically +3.5 dBm. The output power
can be configured via the TX_PWR bits of register PHY_TX_PWR. The output power of
the transmitter can be controlled over a 20 dB range.
A transmission can be started from PLL_ON or TX_ARET_ON state by writing ‘1’ to bit
SLPTR of the TRXPR register or by writing TX_START command to the TRX_CMD bits
of register TRX_STATE.
The PA buffer and PA are enabled sequentially to optimize the output power spectral
density (PSD). A timing example using default settings illustrates the sequence in the
next figure. In this example the transmission is initiated with the rising edge of the
SLPTR bit. The radio transceiver state changes from PLL_ON to BUSY_TX. The
modulation starts 16 µs after SLPTR.
Ext. R F front-end and
Output Power C ontrol
PLL – TX M odulation
Analog D om ain
TX D ata
D igital Dom ain
TX BBP
Control
"Frame Transmit Procedure" on page
R egisters
M em ory
Fram e
Space
Buffer
I/O
8266A-MCU Wireless-12/09
$0140
$017F
$0180
$01FF
µC
I/F