ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 243

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9.8 TIFR0 – Timer/Counter0 Interrupt Flag Register
8266A-MCU Wireless-12/09
• Bit 7:3 – Res4:0 - Reserved
This bit is reserved for future use. A read access always will return zero. A write access
does not modify the content.
• Bit 2 – OCF0B - Timer/Counter0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter0 and
the data in OCR0B Output Compare Register. OCF0B is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared
by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt Enable) and OCF0B are set, the Timer/Counter Compare
Match Interrupt is executed.
• Bit 1 – OCF0A - Timer/Counter0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and
the data in OCR0A Output Compare Register. OCF0A is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared
by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter
Compare A Match Interrupt Enable) and OCF0A are set, the Timer/Counter Compare
Match Interrupt is executed.
• Bit 0 – TOV0 - Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set, the Timer/Counter0
Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit
setting.
Bit
$15 ($35)
Read/Write
Initial Value
Res4
R
7
0
Res3
R
6
0
Res2
R
5
0
Res1
R
4
0
Res0
R
3
0
ATmega128RFA1
OCF0B
RW
2
0
OCF0A
RW
1
0
TOV0
RW
0
0
TIFR0
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