ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 276

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.11.16 TCCR3A – Timer/Counter3 Control Register A
276
ATmega128RFA1
overflows. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt
Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit
location.
• Bit 7:6 – COM3A1:0 - Compare Output Mode for Channel A
The COM3A1:0 bits control the output compare behavior of pin OC3A. If one or both of
the COM3A1:0 bits are written to one, the OC3A output overrides the normal port
functionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC3A pin must be set in order to enable the
output driver. When the OC3A is connected to the pin, the function of the COM3A1:0
bits is dependent of the WGM33:0 bits setting. The following table shows the
COM3A1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-12 COM3A Register Bits
• Bit 5:4 – COM3B1:0 - Compare Output Mode for Channel B
The COM3B1:0 bits control the output compare behavior of pin OC3B. If one or both of
the COM3B1:0 bits are written to one, the OC3B output overrides the normal port
functionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC3B pin must be set in order to enable the
output driver. When the OC3B is connected to the pin, the function of the COM3B1:0
bits is dependent of the WGM33:0 bits setting. The following table shows the
COM3B1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-13 COM3B Register Bits
Bit
NA ($90)
Read/Write
Initial Value
Register Bits
COM3A1:0
Register Bits
COM3B1:0
COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30
RW
7
0
RW
6
0
RW
5
0
Value
Value
0
1
2
3
0
1
2
3
RW
4
0
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on Compare
Match.
Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).
Set OCnA/OCnB/OCnC on Compare Match
(set output to high level).
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on Compare
Match.
Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).
Set OCnA/OCnB/OCnC on Compare Match
RW
3
0
RW
2
0
RW
1
0
8266A-MCU Wireless-12/09
RW
0
0
TCCR3A