ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 162

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

162
ATmega128RFA1
R S T O N
P O R
t
S LEE P
P O R
bandgap
startup
bandgap
startup
t
B G
t
6. SRAM block #3 (upper 4k bytes),
7. Radio transceiver including AES engine,
8. Non-volatile memory.
If the power-chain is completely enabled the standard AVR wake-up procedure
continues.
Figure 12-2 shows the chained startup procedure after power up. A module is only
switched on if it is not deselected by power reduction register (PRR1 or PRR2). This is
possible for SRAM blocks and radio transceiver power switch. At the end of the startup,
the pin RSTON is enabled.
Figure 12-3 shows a similar procedure, the startup from deep sleep.
For further timing information see
page
Figure 12-2. Timing visualization of power up
Figure 12-3. Timing visualization of wakeup from deep sleep
Sleep
Six sleep modes are defined for the CPU. Disabling the power-chain and thus switching
off of the above mentioned blocks makes only sense for the modes “power-down” and
“power-save”. Also an enabled radio transceiver prevents the power-chain from being
disabled.
In order to disable the power-chain, one of the following conditions must fit:
• The radio transceiver has to be disabled (power reduction register PRR1 bit
• The radio transceiver is sent into SLEEP mode (register TRXPR bit SLPTR).
The SRAM blocks may be configured separately to decrease their leakage current (see
section
The following table shows the different implemented sleep modes and the behavior of
the power-chain depending on the current state of the radio transceiver.
Table 12-2. Power states of microcontroller and radio transceiver
B G
AVR State
ON
ON
off
off
PRTRX24).
(1…6)
(1,4…6)
503.
"SRAM with Data Retention" on
D V R E G
startup
t
D V R E G
D V R E G
startup
t
D V R E G
D R T sw itch
S R A M # 0
D R T sw itch
t
S R A M #0
D R T_ O N
t
D R T_ O N
Radio Transceiver State
ON
off (SLEEP or power reduction)
ON
off (SLEEP or power reduction)
D R T sw itch
D R T sw itch
S R A M #1
t
S R AM #1
D R T_ O N
t
D R T_O N
D R T sw itch
"Power Management Electrical Characteristics" on
D R T sw itch
S R A M #2
t
S R A M #2
t
D R T_ O N
D R T _O N
page 163).
t
S T A R T U P
t
S T A R T U P
D R T sw itch
D R T sw itch
S R A M #3
t
S R A M #3
D R T_ O N
t
D R T _O N
pow er sw itch
pow er sw itch
t
radio trans.
t
P W R S W _O N
radio trans.
P W R S W _ O N
pow er sw itch
t
pow er sw itch
t
P W R S W _O N
P W R S W _ O N
N V M
N V M
8266A-MCU Wireless-12/09
Powerchain
ON
ON
ON
ON
t
t
O S C _ S T A R T U P
O S C _S T A R T U P
oscillator
oscillator
startup
startup