ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 169

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.5 TRXPR – Transceiver Pin Register
8266A-MCU Wireless-12/09
• Bit 2 – PRRAM2 - Power Reduction SRAM 2
Setting this bit to one will disable the SRAM block 2. Setting this bit to zero will enable
the SRAM block 2.
• Bit 1 – PRRAM1 - Power Reduction SRAM 1
Setting this bit to one will disable the SRAM block 1. Setting this bit to zero will enable
the SRAM block 1.
• Bit 0 – PRRAM0 - Power Reduction SRAM 0
Setting this bit to one will disable the SRAM block 0. Setting this bit to zero will enable
the SRAM block 0.
The register TRXPR allows to control basic actions of the radio transceiver like reset or
state transitions. The register bit functionality is inherited from the external pins of the
stand-alone radio transceiver.
• Bit 7:4 – Res3:0 - Reserved
• Bit 3:2 – Resx3:2 - Reserved
• Bit 1 – SLPTR - Multi-purpose Transceiver Control Bit
The bit SLPTR is a multi-functional bit to control transceiver state transitions.
Dependent on the radio transceiver state, a rising edge of bit SLPTR causes the
following state transitions: TRX_OFF => SLEEP (level sensitive), PLL_ON =>
BUSY_TX. Whereas the falling edge of bit SLPTR causes the following state transition:
SLEEP => TRX_OFF (level sensitive). When the radio transceiver is in TRX_OFF state
the microcontroller forces the transceiver to SLEEP by setting SLPTR = H. The
Transceiver awakes when the microcontroller releases the bit SLPTR. In states
PLL_ON and TX_ARET_ON, bit SLPTR is used as trigger input to initiate a TX
transaction. Here SLPTR is sensitive on rising edge only. After initiating a state change
by a rising edge at Bit SLPTR in radio transceiver states TRX_OFF, RX_ON or
RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is
logical high and returns to the preceding state with the falling edge.
• Bit 0 – TRXRST - Force Transceiver Reset
The RESET state is used to set back the state machine and to reset all registers of the
transceiver to their default values. A reset forces the radio transceiver into the
TRX_OFF state and resets all transceiver register to their default values. A reset is
initiated with bit TRXRST = H. The bit is cleared automatically During transceiver reset
the microcontroller has to set the radio transceiver control bit SLPTR to the default
value.
Bit
NA ($139)
Read/Write
Initial Value
Res3
R
7
0
Res2
R
6
0
Res1
R
5
0
Res0
R
4
0
Resx3
RW
3
0
ATmega128RFA1
Resx2
RW
2
0
SLPTR
RW
1
0
TRXRST
RW
0
0
TRXPR
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