ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 177

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.1 Power-on Reset
8266A-MCU Wireless-12/09
Figure 13-1. Reset Logic
A Power-on Reset (POR) pulse is generated by a dynamic, on-chip detection circuit.
The POR is active when DEVDD is rising. The electrical characteristics are defined in
"System and Reset Characteristics" on page
trigger the start-up reset. To detect a failure in the supply voltage (e.g. a voltage drop)
the brown-own detector should be used.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes the delay counter, which
determines how long the device is kept in RESET after the DEVDD rise. The RESET
signal is activated again without any delay, when DEVDD decreases below the
detection level.
Figure 13-2. MCU Start-up, RSTN Tied to DEVDD
INTERNAL
TIME-OUT
DEVDD
EVDD
RSTN
DEVDD
RESET
RSTN
BODLEVEL [2..0]
Pull-up Resistor
JTAG Reset
Register
FILTER
SPIKE
V
V
POT
RST
t
CKSEL[3:0]
TOUT
Reset Circuit
Reset Circuit
Reset Circuit
SUT[1:0]
Brown-out
Watchdog
Watchdog
Generator
Power-on
Oscillator
Timer
Clock
CK
Register (MCUSR)
MCU Status
DATA BUS
502. The POR circuit can be used to
Delay Counters
ATmega128RFA1
TIMEOUT
S
R
Q
177