ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 456

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.6.5 Consideration While Updating BLS
30.6.6 Prevent Reading the RWW Section During Self-Programming
30.6.7 Setting the Boot Loader Lock Bits by SPM
30.6.8 EEPROM Write Prevents Writing to SPMCSR
30.6.9 Reading the Fuse and Lock Bits from Software
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ATmega128RFA1
Special care must be taken if the user allows the Boot Loader section to be updated by
leaving Boot Lock bit11 un-programmed. An accidental write to the Boot Loader itself
can corrupt the entire Boot Loader, and further software updates might be impossible. If
it is not necessary to change the Boot Loader software itself, it is recommended to
program the Boot Lock bit11 to protect the Boot Loader software from any internal
software changes.
During Self-Programming (either Page Erase or Page Write), the RWW section is
always blocked for reading. The user software itself must prevent that this section is
addressed during the self programming operation. The RWWSB in the SPMCSR will be
set as long as the RWW section is busy. During Self-Programming the Interrupt Vector
table should be moved to the BLS as described in
interrupts must be disabled. Before addressing the RWW section after the programming
is completed, the user software must clear the RWWSB by writing the RWWSRE. See
"Simple Assembly Code Example for a Boot Loader" on page 458
To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0,
write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR.
Bit
R0
See
the Flash access.
If bits 5:0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it
is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock
bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1”
when writing the Lock bits. When programming the Lock bits the entire Flash can be
read during the operation.
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Signature Row, Fuses and Lock bits from software will also be prevented
during the EEPROM write operation. It is recommended that the user checks the status
bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the
SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR.
When an (E)LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the
destination register. The BLBSET and SPMEN bits will auto-clear upon completion of
reading the Lock bits or if no (E)LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are
cleared, (E)LPM will work as described in the Instruction Set Manual.
Table 31-2 on page 464
7
1
6
1
BLB12
for how the different settings of the Boot Loader bits affect
5
BLB11
4
BLB02
3
BLB01
"Interrupts" on page
2
LB2
1
for an example.
8266A-MCU Wireless-12/09
LB1
0
211, or the