ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 262

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TCNTn and the OCRnx. Note that when working with fixed TOP values, the unused bits
are masked to zero when any of the OCRnx Registers are written. As the third period
shown in Figure 18-8 illustrates, changing the TOP actively while the Timer/Counter is
running in the phase correct mode can result in an asymmetrical output. The reason for
this can be found in the update time of the OCRnx Register. Since the OCRnx update
occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of
the falling slope is determined by the previous TOP value, while the length of the rising
slope is determined by the new TOP value. When these two values are not equal the
two slopes of the period will differ in length. The difference in length gives the
asymmetrical result of the output.
It is recommended to use the phase and frequency correct mode instead of the phase
correct mode when changing the TOP value while the Timer/Counter is running. When
using a static TOP value there are practically no differences between the two modes of
operation.
In phase correct PWM mode, the compare units allow generating PWM waveforms on
the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COMnx1:0 to 3 (see
Table 18-4
on page
256). The actual OCnx value will only be visible on the port pin if the data
direction of the port pin is set to output (DDR_OCnx). The PWM waveform is generated
by setting (or clearing) the OCnx Register at the compare match between OCRnx and
TCNTn when the counter increments, and by clearing (or setting) the OCnx Register at
compare match between OCRnx and TCNTn when the counter decrements. The PWM
frequency of the output f
when using phase-correct PWM can be calculated
OCnxPCPWM
with the following equation:
f
clk
_
I
/
O
f
=
OCnxPCPWM
2
⋅
⋅
)
N
TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11)
and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
18.9.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation (PWM) mode (WGMn3:0 = 8
or 9) provides a high resolution phase and frequency correct PWM waveform
generation option. The phase and frequency correct PWM mode is, like the phase
correct PWM mode, based on a dual-slope operation. The counter counts repeatedly
from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting
Compare Output mode, the Output Compare (OCnx) is cleared on the compare match
between TCNTn and OCRnx while up-counting, and set on the compare match while
down-counting. In inverting Compare Output mode, the operation is inverted. The dual-
slope operation gives a lower maximum operation frequency compared to the single-
slope operation. However these modes are preferred for motor control applications due
to the symmetric feature of the dual-slope PWM modes.
The main difference between the phase correct and the phase and frequency correct
PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register,
(see
Figure 18-8 on page 261
and
Figure 18-9 on page
263).
ATmega128RFA1
262
8266A-MCU Wireless-12/09