ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 489

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.9.12 Programming Algorithm
31.9.13 Entering Programming Mode
31.9.14 Leaving Programming Mode
8266A-MCU Wireless-12/09
During Page Read, the content of the selected Flash byte is captured into the Flash
Data Byte Register during the Capture-DR state. The AVR automatically alternates
between reading the low and the high byte for each new Capture-DR state, starting with
the
PROG_PAGEREAD command. The Program Counter is post-incremented after reading
each high byte, including the first read byte. This ensures that the first data is captured
from the first address set up by PROG_COMMANDS, and reading the last location in
the page makes the program counter increment into the next page.
Figure 31-20. Flash Data Byte Register
The state machine controlling the Flash Data Byte Register is clocked by TCK. During
normal operation in which eight bits are shifted for each Flash byte, the clock cycles
needed to navigate through the TAP-controller automatically feeds the state machine
for the Flash Data Byte Register with sufficient number of clock pulses to complete its
operation transparently for the user. However, if too few bits are shifted between each
Update-DR state during page load, the TAP-controller should stay in the Run-Test/Idle
state for some TCK cycles to ensure that there are at least 11 TCK cycles between
each Update-DR state.
All references below of type “1a”, “1b”, and so on, refer to
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.
Programming Enable Register.
programming Enable Register.
low
byte
for
the
TDO
TDI
D
A
T
A
first
Machine
State
Capture-DR
STROBES
ADDRESS
encountered
ATmega128RFA1
EEPROM
Lock Bits
Fuses
Flash
Table 31-18 on
after
page 485.
entering
the
489