ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 417

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6 Changing Channel or Reference Selection
27.6.1 Accessing the ADMUX Register
8266A-MCU Wireless-12/09
Figure 27-8. ADC Timing Diagram, Free Running Conversion
The MUXn and REFSn bits in the ADMUX and ADCSRB Register are single buffered
through a temporary register to which the CPU has random access. This ensures that
the channels and reference selection only takes place at a safe point during the
conversion. The channel and reference selection is continuously updated either during
the AVDD power-up phase or until a conversion is started by setting ADSC. After this
the channel and reference selection is locked to ensure a sufficient initialization and
sampling time for the ADC. Continuous updating of the channel selection resumes after
the conversion has completed (ADIF in ADCSRA is set). The reference selection can
only be updated if the ADC is disabled and enabled again.
If Auto Triggering is used, the exact time of the triggering event can be undetermined.
Special care must be taken when updating the ADMUX Register, in order to control
which conversion will be affected by the new settings.
If both ADATE and ADEN in the ADSCRA Register are written to one, an interrupt
event can occur at any time. If the ADMUX Register is changed in this period, the user
cannot tell if the next conversion is based on the old or the new settings. ADMUX can
be safely updated in the following ways:
1. When ADATE or ADEN is cleared.
2. During a conversion
3. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next
A/D conversion.
After the channel or reference voltage selection is updated a settling time is required for
the ADC and the gain amplifier or the reference voltage to stabilize. When changing
the channel selection while the ADC is enabled the required settling phase is
automatically inserted by the ADC interface, see section
418. For consideration on changing the reference voltage selection please refer to
section"ADC Voltage Reference" on
The channel selection bits MUX4:0 and MUX5 are located in two different register, the
ADMUX and the ADCSRB register. To ensure that changes go only into effect after
both register have been changed they are internally buffered (see
419 and
write access to the MUX4:0 bits which triggers the update of the internal buffer. If only
A D C C lo c k
A D T S [2 :0 ]
A D S C
A D IF
A D C H
A D C L
Figure 27-10 on
C o n v e rs io n
1 1 T
C o n v e rs io n
C o m p le te
A D C _ C L K
0
page 419). The MUX5 bit has to written first followed by a
M U X a n d R E F S U p d a te
S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt
page 419.
T ra c k in g
t
T R C K
ATmega128RFA1
1 1 T
C o n v e rs io n
"ADC Input Channels" on
A D C _C L K
S a m p le & H o ld
Figure 27-9 on
page
page
417