ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 304

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler
19.1 Internal Clock Source
19.2 Prescaler Reset
19.3 External Clock Source
304
ATmega128RFA1
Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to
all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
prescaler can be used as a clock source. The prescaled clock has a frequency of either
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have
implications for situations where a prescaled clock is used. One example of prescaling
artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 >
1). The number of system clock cycles from the moment the timer is enabled until the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the
prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However care must be taken if the other Timer/Counter that shares the same
prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all
connected Timer/Counters.
An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
Figure 19-1 shows a functional equivalent block diagram of the Tn synchronization and
edge detector logic. The registers are clocked at the positive edge of the internal
system clock (clk
clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 19-1. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge applied to the Tn pin to the counter being updated.
CLK_I/O
Tn
clk
Tn
I/O
). The Tn pin is sampled once every system clock cycle by the pin synchronization
/8, f
CLK_I/O
D
LE
/64, f
I/O
Q
). The latch is transparent in the high period of the internal system
CLK_I/O
Synchronization
D
/256 or f
Q
CLK_I/O
Tn
CLK_I/O
pulse for each positive (CSn2:0 = 7) or negative
/1024.
). Alternatively one of four taps from the
D
Q
8266A-MCU Wireless-12/09
Edge Detector
Tn_sync
(To Clock
Select Logic)