ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 128

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.12.45 CSMA_SEED_0 – Transceiver CSMA-CA Random Number Generator Seed Register
128
ATmega128RFA1
Table 9-67 MAX_CSMA_RETRIES Register Bits
• Bit 0 – SLOTTED_OPERATION - Set Slotted Acknowledgment
When using RX_AACK mode in networks operating in beacon or slotted mode
according
SLOTTED_OPERATION indicates that acknowledgment frames are to be sent on back-
off slot boundaries (slotted acknowledgment). If this register bit is set the
acknowledgment frame transmission has to be initiated by the application software
using bit SLPTR of register TRXPR. This waiting state is signaled in sub register
TRAC_STATUS of register TRX_STATE with value SUCCESS_WAIT_FOR_ACK.
Table 9-68 SLOTTED_OPERATION Register Bits
This register contains the lower 8 bits of the CSMA_SEED. The upper 3 bits are part of
register CSMA_SEED_1. CSMA_SEED is the seed for the random number generation
that determines the length of the back-off period in the CSMA-CA algorithm. It is
recommended to initialize registers CSMA_SEED by random values. This can be done
using the bits RND_VALUE of register PHY_RSSI.
• Bit 7:0 – CSMA_SEED_07:00 - Seed Value for CSMA Random Number
These bits contain the bits [7:0] of the CSMA_SEED.
Bit
NA ($16D)
Read/Write
Initial Value
Register Bits
MAX_CSMA_RETRIES2:0
Register Bits
SLOTTED_OPERATION
Generator
RW
to
7
1
IEEE
RW
6
1
RW
802.15.4-2006,
5
1
CSMA_SEED_07:00
Value
Value
RW
0x0
0x1
0x2
0x5
0x6
0x7
4
0
0
1
RW
3
1
Description
No repetition of CSMA-CA procedure
One repetition of CSMA-CA procedure
...
Five repetitions (highest IEEE 802.15.4
compliant value)
Reserved
Immediate frame re-transmission without
performing CSMA-CA
Description
The radio transceiver operates in unslotted
mode. An acknowledgment frame is
automatically sent if requested.
The transmission of an acknowledgment
frame has to be controlled by the
microcontroller.
chapter
RW
2
0
RW
1
1
5.5.1
RW
0
0
the
8266A-MCU Wireless-12/09
CSMA_SEED_0
register
bit