ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 49

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.2.3.1 Description of RX_AACK Configuration Bits
8266A-MCU Wireless-12/09
Overview
The following table summarizes all register bits which affect the behavior of a
RX_AACK transaction. For address filtering it is further required to setup address
registers to match to the expected address.
Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to
switching to RX_AACK mode.
A graphical representation of various operating modes is illustrated in
page 48.
Table 9-5. Overview of RX_AACK Configuration Bits
The usage of the RX_AACK configuration bits for various operating modes of a node is
explained in the following sections. Configuration bits not mentioned in the following two
sections should be set to their reset
All registers mentioned in
on
Note, that the general behavior of the Extended Feature Set settings:
• OQPSK_DATA_RATE
• SFD_VALUE
• ANT_DIV
• RX_PDT_LEVEL
are completely independent from RX_AACK mode (see
Feature Set" on page 85).
RX_AACK mode.
AACK_UPLD_RES_FT
SLOTTED_OPERATION
AACK_FLTR_RES_FT
AACK_I_AM_COORD
AACK_PROM_MODE
page 60.
SHORT_ADDR_0/1
AACK_FVN_MODE
AACK_ACK_TIME
RX_SAFE_MODE
AACK_DIS_ACK
PAN_ADDR_0/1
AACK_SET_PD
Register Name
IEEE_ADDR_0
IEEE_ADDR_7
…
Table 9-5 above
Register Bits
Each of these operating modes can be combined with the
7:6
(PSDU data rate)
(alternative SFD value)
(Antenna Diversity)
(blocking frame reception of lower power signals)
7
1
2
4
5
0
3
4
5
values.
Description
Set node addresses
Protect buffer after frame receive
Support promiscuous mode
Change auto acknowledge start time
Enable reserved frame type reception, needed to
receive non-standard compliant frames
Filter reserved frame types like data frame type,
needed for filtering of non-standard compliant
frames
If set, acknowledgment transmission has to be
triggered by register bit SLPTR
If set, the device is a PAN coordinator
Disable generation of acknowledgment
Set frame pending subfield in Frame Control Field
(FCF), refer to section
Controls the ACK behavior, depending on FCF
frame version number
are described in section
ATmega128RFA1
"Radio Transceiver Extended
"Overview" on page 66
"Register Summary"
Figure 9-19 on
49