ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 342

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.3.2 Double Speed Operation (U2Xn)
23.3.3 External Clock
23.3.4 Synchronous Clock Operation
342
ATmega128RFA1
BAUD
f
UBRRn
Some examples of UBRRn values for some system clock frequencies are found in
Table 23-14 on page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit
only has effect for the asynchronous operation. Set this bit to zero when using
synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the transmitter, there are no
downsides.
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to
External clock input from the XCKn pin is sampled by a synchronization register to
minimize the chance of meta-stability. The output from the synchronization register
must then pass through an edge detector before it can be used by the transmitter and
receiver. This process introduces a two CPU clock period delay and therefore the
maximum external XCKn clock frequency is limited by the following equation:
Note that f
recommended to add some margin to avoid possible loss of data due to frequency
variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either
clock input (slave) or clock output (master). The dependency between the clock edges
and data sampling or data change is the same. The basic principle is that data input (on
RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn)
is changed.
OSC
Operating Mode
Synchronous Master Mode
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps).
OSC
Baud rate (in bits per second, bps)
System oscillator clock frequency
Contents of the UBRRHn and UBRRLn registers, (0-4095)
depends on the stability of the system clock source. It is therefore
365.
Figure 22-2 on page 331
Equation for Calculating
Baud Rate
BAUD
f
=
XCK
(1)
( 2
UBRRn
<
f
f
OSC
OSC
4
for details.
+
) 1
Equation for Calculating
UBRR Value
UBRRn
8266A-MCU Wireless-12/09
=
2
BAUD
f
OSC
−
1