ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZU

Manufacturer Part Number
ATMEGA128RFA1-ZU
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZU

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Rf Ic Case Style
QFN
No. Of Pins
64
Supply Voltage Range
1.8V To 3.6V
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA128RFA1-ZU
Manufacturer:
ATMEL
Quantity:
3 645
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
8266B-MCU Wireless-03/11
Features
• High Performance, Low Power AVR
• Advanced RISC Architecture
• Non-volatile Program and Data Memories
• JTAG (IEEE std. 1149.1 compliant) Interface
• Peripheral Features
• Advanced Interrupt Handler
• Watchdog Timer with Separate On-Chip Oscillator
• Power-on Reset and Low Current Brown-Out Detector
• Advanced Power Save Modes
• Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
• Hardware Security (AES, True Random Generator)
• Integrated Crystal Oscillators (32.768 kHz & 16 MHz, external crystal needed)
• I/O and Package
• Temperature Range: -40° C to 125° C Industrial
• Supply voltage range 1.8V to 3.6V with integrated voltage regulators
• Ultra Low Power consumption (1.8 to 3.6V) for Rx/Tx & AVR: <18.6 mA
• Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V
Applications
• ZigBee
• General Purpose 2.4GHz ISM Band Transceiver with Microcontroller
• RF4CE, SP100, WirelessHART
- 135 Powerful Instructions – Most Single Clock Cycle Execution
- 32x8 General Purpose Working Registers
- Fully Static Operation
- Up to 16 MIPS Throughput at 16 MHz and 1.8V
- On-Chip 2-cycle Multiplier
- 128K Bytes of In-System Self-Programmable Flash
- 4K Bytes EEPROM
- 16K Bytes Internal SRAM
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug Support
- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface
- Multiple Timer/Counter & PWM channels
- Real Time Counter with Separate Oscillator
- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor
- Master/Slave SPI Serial Interface
- Two Programmable Serial USART
- Byte Oriented 2-wire Serial Interface
- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm
- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
- 32 Bit IEEE 802.15.4 Symbol Counter
- Baseband Signal Processing
- SFR-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation
- Antenna Diversity and TX/RX control
- TX/RX 128 Byte Frame Buffer
- 38 Programmable I/O Lines
- 64-pad QFN (RoHS/Fully Green)
- CPU Active Mode (16MHz): 4.1 mA
- 2.4GHz Transceiver: RX_ON 12.5 mA / TX 14.5 mA (maximum TX output power)
- Deep Sleep Mode: <250nA @ 25° C
• Endurance: 1000 Write/Erase Cycles @ 125° C (2000 Cycles @ 85° C)
• Endurance: 1000 Write/Erase Cycles @ 125° C (2000 Cycles @ 85° C)
®
/ IEEE 802.15.4-2006/2003
, ISM Applications and IPv6 / 6LoWPAN
®
8-Bit Microcontroller
– Full And Reduced Function Device (FFD/RFD)
ATmega128RFA1
8-bit
Microcontroller
with Low Power
2.4GHz
Transceiver for
ZigBee and
IEEE 802.15.4
ATmega128RFA1
PRELIMINARY
8266B-MCU Wireless-03/11
1

Related parts for ATMEGA128RFA1-ZU

ATMEGA128RFA1-ZU Summary of contents

Page 1

... General Purpose 2.4GHz ISM Band Transceiver with Microcontroller ™ • RF4CE, SP100, WirelessHART 8266B-MCU Wireless-03/11 ® 8-Bit Microcontroller ™ – Full And Reduced Function Device (FFD/RFD) , ISM Applications and IPv6 / 6LoWPAN ATmega128RFA1 8-bit Microcontroller with Low Power 2.4GHz Transceiver for ZigBee and IEEE 802.15.4 ATmega128RFA1 PRELIMINARY 8266B-MCU Wireless-03/11 1 ...

Page 2

... Pin Configurations [PF2:ADC2:DIG2] [PF3:ADC3:DIG4] [PF4:ADC4:TCK] [PF5:ADC5:TMS] [PF6:ADC6:TDO] [PF7:ADC7:TDI] [AVSS_RFP] [AVSS_RFN] [RSTN] [RSTON] [PG0:DIG3] [PG1:DIG1] [PG2:AMR] 2 Disclaimer ATmega128RFA1 2 Figure 1-1. Pinout ATmega128RFA1 Index corner ATmega128RFA1 7 [RFP] 8 [RFN [TST Exposed paddle: [AVSS Note: The large center pad underneath the QFN/MLF package is made of metal and internally connected to AVSS ...

Page 3

... Overview 3.1 Block Diagram 8266B-MCU Wireless-03/11 The ATmega128RFA1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz ISM band derived from the ATmega1281 microcontroller and the AT86RF231 radio transceiver. ...

Page 4

... Spectrum Signal (DSSS) processing with spreading and despreading. The device is fully compatible with IEEE802.15.4-2006/2003 and ZigBee standards. The ATmega128RFA1 provides the following features: 128 kbytes of In-System Programmable (ISP) Flash with read-while-write capabilities, 4 kbytes EEPROM, 16 kbytes SRAM general purpose I/O lines, 32 general purpose working ...

Page 5

... Read-While-Write operation. By combining an 8 bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128RFA1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128RFA1 AVR is supported with a full suite of program and system development tools including: debugger/simulators, in-circuit emulators, and evaluation kits ...

Page 6

... The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also provides functions of various special features of the ATmega128RFA1. AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port. ...

Page 7

... XTAL1 and XTAL2 shall never be forced to supply voltage at the same time. The basic AVR feature set of the ATmega128RFA1 is derived from the ATmega1281/2561. Address locations and names of the implemented modules and registers are unchanged as long as it fits the target application of a very small and power efficient radio system ...

Page 8

... Data Retention and Endurance 6.1 Data Retention 6.2 Endurance of the Code Memory (FLASH) 6.3 Endurance of the Data Memory (EEPROM) ATmega128RFA1 8 This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent ...

Page 9

... While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATmega128RFA1 Data Bus 8-bit Status and Control ...

Page 10

... Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega128RFA1 has Extended I/O space from 0x60 - 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

Page 11

... The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. • Bit 0 – Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically ATmega128RFA1 ...

Page 12

... General Purpose Register File 7.5.1 The X-register, Y-register, and Z-register ATmega128RFA1 12 stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • ...

Page 13

... The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. • Bit 7:0 – SP15:8 - Stack Pointer High Byte ATmega128RFA1 ...

Page 14

... SPL – Stack Pointer Low 7.6.3 RAMPZ – Extended Z-pointer Register for ELPM/SPM ATmega128RFA1 14 Bit $3D ($5D) SP7 SP6 SP5 Read/Write Initial Value The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed ...

Page 15

... Boot Flash section by programming the BOOTRST Fuse, see "Memory Programming" on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested ATmega128RFA1 " ...

Page 16

... ATmega128RFA1 16 interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag ...

Page 17

... This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set. ATmega128RFA1 17 ...

Page 18

... Boot Program section and Application Program section. The Flash memory has an endurance of at least 2000 write/erase cycles. The ATmega128RFA1 Program Counter (PC bits wide, thus addressing the required program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Read-While-Write Self-Programming" ...

Page 19

... When using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM in the ATmega128RFA1 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page Figure 8-7 ...

Page 20

... Data RD Memory Access Instruction The ATmega128RFA1 contains 4Kbyte of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

Page 21

... Erase is controlled with r20 and r21 ldi r20, (1<<EEMPE) + (1<<EEPM0) ldi r21, (1<<EEMPE) + (1<<EEPE) + (1<<EEPM0) ; Start eeprom erase out EECR, r20 out EECR, r21 ret ; main program … ldi r17, addr_low ldi r18, addr_high call EEPROM_erase ldi r16, ee_data ATmega128RFA1 21 ...

Page 22

... ATmega128RFA1 22 call EEPROM_write … C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous erase/write */ while(EECR & (1<<EEPE Set up address */ EEAR = uiAddress; EEDR = 255; /* Write logical one to EEMPE and enable erase only*/ EECR = (1<<EEMPE) + (1<<EEPM0); ...

Page 23

... Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; } ATmega128RFA1 23 ...

Page 24

... EEPROM Register Description 8.4.1 EEARH – EEPROM Address Register High Byte 8.4.2 EEARL – EEPROM Address Register Low Byte ATmega128RFA1 24 During periods of low DEVDD, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied ...

Page 25

... EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure. • Bit 1 – EEPE - EEPROM Programming Enable ATmega128RFA1 ...

Page 26

... The Input/Output (I/O) space definition of the ATmega128RFA1 is shown in Summary" on page 498. All ATmega128RFA1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 – ...

Page 27

... GPIOR2 – General Purpose I/O Register 2 8266B-MCU Wireless-03/11 0x20 must be added to these addresses. The ATmega128RFA1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – ...

Page 28

... Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value The inherited control registers of missing ports located in the I/O space are kept in the ATmega128RFA1. They can be used as general purpose I/O registers for storing any information. Registers placed in the address range 0x00 – 0x1F are directly bit- accessible using the SBI, CBI, SBIS and SBIC instructions ...

Page 29

... Bit 7:0 – DDC7:0 - Port C Data Direction Register Value Bit $06 ($26) Read/Write Initial Value The PINC register is reserved for interal use and cannot be used as a General Purpose I/O Register. • Bit 7:0 – PINC7:0 - Port C Input Pins ATmega128RFA1 PORTC7 ...

Page 30

... Low-Power 2.4 GHz Transceiver 9.1 Features ATmega128RFA1 30 • High performance RF-CMOS 2.4 GHz radio transceiver targeted for IEEE 802.15.4™, ZigBee™, IPv6 / 6LoWPAN, RF4CE, SP100, WirelessHART™ and ISM applications • Outstanding link budget (103.5 dB): Receiver sensitivity -100 dBm o Programmable output power from -17 dBm up to +3.5 dBm o • ...

Page 31

... DIG1/2 Analog Domain 8266B-MCU Wireless-03/11 The ATmega128RFA1 features a low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true peripheral block of the AVR microcontroller. All RF-critical components except the antenna, crystal and de- coupling capacitors are integrated on-chip ...

Page 32

... Transceiver to Microcontroller Interface 9.3.1 Transceiver Configuration and Data Access 9.3.1.1 Register Access ATmega128RFA1 32 The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (RX ADC) and generates a digital RSSI signal ...

Page 33

... The Transceiver Pin Register TRXPR is located in the Controller clock domain and is accessible even if the transceiver is in sleep state. This register provides access to the pin functionality, known from the RF231 devices (two chip solution). ATmega128RFA1 "Frame Buffer" on page 62. "Link Quality Indication (LQI)" on page 73 " ...

Page 34

... Sleep SLEEP Wakeup 9.3.2 Interrupt Logic 9.3.2.1 Overview ATmega128RFA1 34 The register (TRXRST) can be used to reset the transceiver without resetting the controller. After the reset bit was set cleared immediately. A second configuration bit (SLPTR) is used to control frame transmission or sleep and wakeup of the transceiver. This bit is not cleared automatically. ...

Page 35

... The interrupt handling in Extended Operating Mode is described in section Handling" on page 60. The ATmega128RFA1 Transceiver module can be identified by four registers (PART_NUM, VERSION_NUM, MAN_ID_0, MAN_ID_1). One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JTAG manufacture ID. The transceiver identification registers are provided for compatibility to the transceiver only device ...

Page 36

... 9.4.1.1 State Control ATmega128RFA1 36 This section summarizes all states to provide the basic functionality of the 2.4GHz radio transceiver, such as receiving and transmitting frames, the power up sequence and radio transceiver sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the corresponding radio transceiver states are shown in below ...

Page 37

... SLPTR and TRXRST in register TRXPR can be used for state control (see Control" on page 36 for details). The analog front-end is disabled during TRX_OFF. Entering the TRX_OFF state from radio transceiver SLEEP, or RESET state is indicated by the TRX24_AWAKE interrupt. ATmega128RFA1 "Transceiver Pin Register TRXPR" on 93). "State 37 ...

Page 38

... PLL_ON – PLL State 9.4.1.2.4 RX_ON and BUSY_RX – RX Listen and Receive State 9.4.1.2.5 BUSY_TX – Transmit State ATmega128RFA1 38 Entering the PLL_ON state from TRX_OFF state first enables the analog voltage regulator (AVREG). After the voltage regulator has been settled the PLL frequency synthesizer is enabled ...

Page 39

... The RESET state is used to set back the state machine and to reset all registers of the radio transceiver to their default values. A reset forces the radio transceiver into the TRX_OFF state. A reset is initiated by a ATmega128RFA1 main reset (see 177 radio transceiver reset (see During radio transceiver reset the TRXPR register is not cleared and therefore the application software has to set the SLPTR bit to “ ...

Page 40

... Figure 9-13. Timing of TRX24_RX_START, TRX24_XAH_AMI, TRX24_TX_END and TRX24_RX_END Interrupts in Basic Operating Mode - µ 9.4.1.4 Basic Operating Mode Timing 9.4.1.4.1 Wake-up Procedure ATmega128RFA1 The following paragraphs depict state transitions and their timing properties. Timing figures are explained in Table 9-3 on Characteristics" on page 511. ...

Page 41

... TX_START Tim e Starting from PLL_ON state it is assumed that the PLL is already locked. A transmission is initiated either by writing “1” to bit SLPTR or by command TX_START. The PLL settles to the transmit frequency and the PA is enabled. ATmega128RFA1 100 TRX24_PLL_LOCK IRQ PLL_ON RX_ON ...

Page 42

... Reset Procedure ATmega128RFA1 µs after initiating the transmission, the radio transceiver changes into TR10 BUSY_TX state and the internally generated SHR is transmitted. After that the PSDU data are transmitted from the Frame Buffer. After completing the frame transmission, indicated by the TRX24_TX_END interrupt, ...

Page 43

... ATmega128RFA1 Table 9-3 below. See measurement setup in Comments Depends on crystal oscillator setup ( pf) TRX_OFF state indicated by TRX24_AWAKE interrupt For f > 250 kHz CLKM Depends on external capacitor at AVDD (1 µF nom) Depends on external capacitor at AVDD (1 µF nom) Transition time is also valid for TX_ARET_ON, RX_AACK_ON When setting bit SLPTR or TRX_CMD = TX_START, the first symbol transmission is delayed by 16 µ ...

Page 44

... SHR, sync TR27 28 t CCA TR28 29 t Random value TR29 9.4.2 Extended Operating Mode ATmega128RFA1 44 Time [µs], (typ) Time [µs], (max) Comments 32 2 140 96 140 1 The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks requested by the IEEE 802 ...

Page 45

... Table 9-16 on page 59. The state diagram including the Extended Operating Mode states is shown in 18 below. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode rom / Note: 1. State transition numbers correspond to ATmega128RFA1 (fro sta see notes ...

Page 46

... State Control 9.4.2.2 Configuration ATmega128RFA1 46 The Extended Operating Mode states RX_AACK and TX_ARET are controlled via the bits TRX_CMD of register TRX_STATE, which receives the state transition commands. The states are entered from TRX_OFF or PLL_ON state as illustrated in page 45. The completion of each state change command shall always be confirmed by reading the TRX_STATUS register ...

Page 47

... The frame filtering operation is described in detail in section 55. In RX_AACK_ON state, the radio transceiver listens for incoming frames. After detecting SHR and a valid PHR, the radio transceiver parses the frame content of the MAC header (MHR) as described in section ATmega128RFA1 "Description of RX_AACK Configuration Bits" on register TRX_CTRL_1 register XAH_CTRL_0 register XAH_CTRL_0 ...

Page 48

... ATmega128RFA1 48 Generally, at nodes, configured as a normal device or PAN coordinator, a frame is not indicated if the frame filter does not match and the FCS is invalid. Otherwise, the TRX_24_RX_END interrupt is issued after the completion of the frame reception. The microcontroller can then read the frame. An exception applies if promiscuous mode is enabled (see section " ...

Page 49

... Note 2) Y Generate TRX24_RX_END interrupt N ACK requested (see Note Slotted Operation == AACK_ACK_TIME == Wait 12 symbol periods periods N Transmit ACK GenerateTRX24_TX_END interrupt TRX_STATE = RX_AACK_ON ATmega128RFA1 Promiscuous Mode Frame reception N AACK_PROM_MODE == AACK_UPLD_RES_FT N Generate TRX24_RX_END interrupt Wait 2 symbol periods Reserved Frames FCF[2:0] > FCS valid Y Generate TRX24_RX_END ...

Page 50

... Description of RX_AACK Configuration Bits ATmega128RFA1 50 Overview The following table summarizes all register bits which affect the behavior of a RX_AACK transaction. For address filtering it is further required to setup address registers to match to the expected address. Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to switching to RX_AACK mode ...

Page 51

... IEEE 802.15.4-2006 standard compliant networks. The same holds for PAN coordinators as described below. PAN-Coordinator Table 9-7 on page 52 shows the RX_AACK configuration for a PAN coordinator. ATmega128RFA1 Description Set node addresses 0: disable frame protection 1: enable frame protection 0: if transceiver works in unslotted mode ...

Page 52

... ATmega128RFA1 52 Table 9-7. Configuration of a PAN Coordinator Register Name Register Bits SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 RX_SAFE_MODE 7 SLOTTED_OPERATION 0 AACK_I_AM_COORD 3 AACK_SET_PD 5 AACK_FVN_MODE 7:6 Promiscuous Mode The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.5. This mode is further illustrated in Radio Transceiver Extended Feature Set on page to IEEE 802 ...

Page 53

... Register Name Register Bits AACK_PROM_MODE 1 AACK_DIS_ACK 4 This operating mode is similar to the promiscuous mode. ATmega128RFA1 Description Controls the ACK behavior, depends on FCF frame version number 0x00 : acknowledges only frames with version number 0, i.e. according to IEEE 802.15.4-2003 frames 0x01 : acknowledges only frames with version number ...

Page 54

... ATmega128RFA1 54 Reception of Reserved Frames Frames with reserved frame types (see section handled in RX_AACK mode. This might be required when implementing proprietary, non-standard compliant protocols extension of the address filtering in RX_AACK mode. Received frames are either handled similar to data frames or may be allowed to completely bypass the address filter. ...

Page 55

... PAN identifier matches macPANId. The radio transceiver requires two additional rules: 1. The frame type indicates that the frame is not an ACK frame (refer page 51). ATmega128RFA1 Description 0: Standard compliant acknowledgement timing of 12 symbol periods. In slotted acknowledgement operation mode, the acknowledgment frame transmission can be triggered 6 symbol periods after reception of the frame earliest ...

Page 56

... RX_AACK Slotted Operation – Slotted Acknowledgement ATmega128RFA1 least one address field must be configured. Address match, indicated by the TRX24_AMI interrupt is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: If (Destination Addressing Mode = AND (Source Addressing Mode = 0) no ...

Page 57

... Interface Timing Characteristics" on page 512 D ata F ram e (Length = 10 bit AACK_ACK_TIME of register XAH_CTRL_1 is set, an acknowledgment frame is sent already 2 symbol times after the reception of the last symbol of a data or MAC command frame. ATmega128RFA1 ram 24_R µ transm ission initiated by m icrocontroller IRQ 511 ...

Page 58

... TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry Figure 9-12. Flow Diagram of TX_ARET fra rctr = MAX_CSM A_RETRIES < rctr = rctr + fra fra rctr + ste til tim lid N N fra > ATmega128RFA1 try rfo rctr > ilu re MAX_CSMA_RETRIES rru 8266B-MCU Wireless-03/11 ...

Page 59

... Table 9-16. Interpretation of the TRAC_STATUS register bits Value Name 0 SUCCESS 1 SUCCESS_DATA_PENDING 3 CHANNEL_ACCESS_FAILURE ATmega128RFA1 Figure 9-12 on page 58. or writing a Description The transaction was responded by a valid ACK, or ACK is requested, after a successful frame transmission Equivalent to SUCCESS; indicates pending frame data according to the MHR frame ...

Page 60

... TRX_STATE TX_ARET_ON RX/TX CSMA-CA SLPTR IRQ Typ. Processing Delay t CSM A-CA 9.4.2.6 Interrupt Handling ATmega128RFA1 60 Value Name 5 NO_ACK 7 INVALID Note that if no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues a TRX24_TX_END interrupt directly after the frame transmission has been completed ...

Page 61

... Radio transceiver state control, TX_ARET status TRX_CTRL_1 TX_AUTO_CRC_ON PHY_CC_CCA CCA mode control, CCA_THRES CCA threshold settings, see XAH_CTRL_1 RX_AACK control ATmega128RFA1 Description Indicates a PHR reception Issued at address match Signals completion of RX_AACK transaction if successful A received frame must pass the address filter; - The FCS is valid ...

Page 62

... Functional Description 9.5.1 Introduction – IEEE 802.15.4-2006 Frame Format Figure 9-14. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU) 9.5.1.1 PHY Protocol Layer Data Unit (PPDU) 9.5.1.1.1 Synchronization Header (SHR) 9.5.1.1.2 PHY Header (PHR) ATmega128RFA1 62 Register Name Description IEEE_ADDR7 …. ...

Page 63

... Figure 9-15 below shows the frame structure of the MAC layer. The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields (which are of variable length and can even be empty in certain situations). ATmega128RFA1 Payload Reserved MPDU (Acknowledgement) Reserved ...

Page 64

... Frame Control Field (FCF) ATmega128RFA1 64 The FCF consists of 16 bits, and occupies the first two octets of either the MPDU or the PSDU, respectively. Figure 9-26. IEEE 802.15.4-2006 Frame Control Field (FCF) Bit [2:0]: describe the frame type. by IEEE 802.15.4, section 7.2.1.1.1. ...

Page 65

... Addressing Mode” (refer to The subfields of the FCF (Bits 0– 10–15) affect the address filter logic of the radio transceiver while executing a RX_AACK operation (see Receive with Automatic ACK" on page ATmega128RFA1 Description PAN identifier and address fields are not present Reserved ...

Page 66

... Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 9.5.1.2.4 Sequence Number 9.5.1.2.5 Addressing Fields 9.5.1.2.6 Auxiliary Security Header Field ATmega128RFA1 66 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the “Channel Page” field present (see IEEE 802.15.4- 2006 7 ...

Page 67

... Divide modulo 2 by the generator polynomial G polynomial ... 0 1 The FCS field is given by the coefficients of the remainder polynomial, R(x). ATmega128RFA1 "Frame Compatibility between IEEE 802.15.4- page 66). For details of its structure see below. can be disabled − − 1 (x) to obtain the remainder ...

Page 68

... Automatic FCS generation 9.5.2.4 Automatic FCS check 9.5.3 Received Signal Strength Indicator (RSSI) 9.5.3.1 Overview ATmega128RFA1 68 Example: Consider a 5 octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. The leftmost bit ( transmitted first in time. The FCS is in this case 0 0010 0111 1001 1110 ...

Page 69

... The receiver ED measurement is used by the network layer as part of a channel selection algorithm estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128 µs). ATmega128RFA1 for details. < -90 dBm. For an RSSI RF 10 ...

Page 70

... Measurement Description 9.5.4.3 Data Interpretation ATmega128RFA1 70 For High Data Rate Modes the automated ED measurement duration is reduced to 32 µs as described in "High Data Rate Modes" on page these modes is still 128 µs for manually initiated ED measurements as long as the receiver is in RX_ON state. There are two ways to initiate an ED measurement: • ...

Page 71

... CCA shall report a busy medium upon detecting any energy above the ED threshold. 2 Carrier sense only. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED threshold. ATmega128RFA1 Register PHY_ED_LEVEL Value 70 ...

Page 72

... Configuration and CCA Request 9.5.5.3 Data Interpretation 9.5.5.4 Interrupt Handling ATmega128RFA1 72 CCA Mode Description 0, 3 Carrier sense with energy above threshold. CCA shall report a busy medium using a logical combination of Detection of a signal with the modulation and spreading characteristics of - this standard and Energy above the ED threshold ...

Page 73

... LQI values in between should be uniformly distributed between these two limits. The LQI measurement of the radio transceiver is implemented as a measure of the link quality which can be described with the packet error rate (PER) of this link. A LQI value ATmega128RFA1 "Configuration and CCA Table 9-22 below. ...

Page 74

... Request a LQI Measurement 9.5.6.3 Data Interpretation ATmega128RFA1 74 can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value ...

Page 75

... The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital ATmega128RFA1 "I/O Memory" on page igital D om ain ...

Page 76

... Frame Receive Procedure 9.6.1.3 Configuration ATmega128RFA1 76 converter (RX ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The receiver is designed to handle frequency and symbol rate deviations up to ± ...

Page 77

... A timing example using default settings illustrates the sequence in the next figure. In this example the transmission is initiated with the rising edge of the SLPTR bit. The radio transceiver state changes from PLL_ON to BUSY_TX. The modulation starts 16 µs after SLPTR. ATmega128RFA1 Control R egisters Fram e ...

Page 78

... PLL_O N TRX_STATE SLPTR PA buffer PA M odulation 9.6.3 Frame Buffer 9.6.3.1 Data Management ATmega128RFA1 SY_TX When using an external RF front-end (refer to required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved using register bits PA_BUF_LT and PA_LT of register PHY_TX_PWR ...

Page 79

... Frame Buffer. The frame length information is located in register TST_RX_LENGTH. The SHR (except the SFD used to generate the last octet of the SHR) can generally not be read by the application software. ATmega128RFA1 "Dynamic Frame Buffer Protection" on page "TX_ARET_ON – 58) the radio transceiver ...

Page 80

... Battery Monitor (BATMON) 9.6.4.1 Overview 9.6.4.2 Configuration 9.6.4.3 Data Interpretation ATmega128RFA1 80 The PHR and the PSDU need to be stored in the Frame Buffer for frame transmission. The PHR byte is the first byte in the Frame Buffer (address 0x180) and must be calculated based on the PHR and the PSDU. The maximum frame size supported by the radio transceiver is 128 bytes ...

Page 81

... The output frequency of the internal oscillator depends on the load capacitance between the crystal pins XTAL1 and XTAL2. The total load capacitance C equal to the specified load capacitance of the crystal itself. It consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes. ATmega128RFA1 page 82. Nevertheless a reference frequency can Figure must be ...

Page 82

... External Reference Frequency Setup ATmega128RFA1 82 The following figure shows all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance summarized to C Figure 9-25. Simplified XOSC Schematic with External Components C CX PAR V EVDD 16MHz XTAL1 EVDD C TRIM XTAL_TRIM[3:0] EVDD Additional internal trimming capacitors ...

Page 83

... TRX_OFF to PLL_ON. The center frequency calibration is additionally initiated when the PLL changes to a center frequency of another channel recommended to initiate the calibration loops manually if the PLL operates for a long time on the same channel e.g. more than 5 min or the operating temperature ATmega128RFA1 XTAL2 PCB IC internal Table 9-8 on page 43Table 9-8) ...

Page 84

... Interrupt Handling 9.6.6.5 RF Channel Selection 9.6.7 Automatic Filter Tuning (FTN) 9.7 Radio Transceiver Usage ATmega128RFA1 84 changes significantly. Both calibration loops can be initiated manually by setting PLL_CF_START = 1 of register PLL_CF and PLL_DCU_START = 1 of register PLL_DCU. The device must be in PLL_ON or RX_ON state to start the calibration. The completion of the center frequency tuning is indicated by a TRX24_PLL_LOCK interrupt ...

Page 85

... A frame transmission comprises of the two actions Frame Buffer write access and transmission of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. Figure 9-28 on page 86 illustrates the frame transmit procedure by consecutively writing and transmitting the frame. The frame transmission is initiated writing SLPTR or writing ATmega128RFA1 (Register access) 85 ...

Page 86

... Radio Transceiver Extended Feature Set 9.8.1 Random Number Generator ATmega128RFA1 86 command TX_START to register TRX_STATE after a Frame Buffer write access and while the radio transceiver is in state PLL_ON or TX_ARET_ON. The TRX24_TX_END interrupt indicates the completion of the transaction. Figure 9-28. Transaction between radio transceiver and microcontroller during transmit ...

Page 87

... IEEE 802.15.4 compliant data rate of 250 kb/s (refer to 2006 Frame Format" on page 62). A comparison of the general packet structure for different data rates with an example PSDU length of 80 octets is shown in ATmega128RFA1 "Security Module (AES)" on Comment PER 1%, PSDU length of 20 octets PER ...

Page 88

... PSDU: 80 octets 2000 kb/s PSDU: 80 octets 9.8.2.3 High Data Rate Frame Buffer Access 9.8.2.4 High Data Rate Energy Detection ATmega128RFA1 88 832 1472 The effective data rate is smaller than the selected data rate due to the overhead caused by the SHR, the PHR and the FCS. The overhead depends further on the length of the PSDU ...

Page 89

... These fading effects can result in an increased error floor or loss of the connection between devices. Antenna Diversity can be applied to reduce the effects of multipath propagation and fading hence improving the reliability connection between network nodes. ATmega128RFA1 "Current Consumption 47), the acknowledgment frame response time illustrates an example for a reception and ...

Page 90

... Antenna Diversity Application Example ATmega128RFA1 90 Antenna Diversity uses two antennas to switch to the most reliable RF signal path. This is done by the radio transceiver during RX_LISTEN and RX_AACK_ON state without interaction of the application software. Both antennas should be carefully separated from each other to ensure highly independent receive signals. ...

Page 91

... RF switches and other building blocks especially during sleep modes. The setup time of the external power amplifier (PA) relative to the internal building blocks should be adjusted when using an external RF front-end including a power amplifier to optimize the overall power spectral density (PSD) mask. ATmega128RFA1 91 ...

Page 92

... It is not recommended to set the low-order 4 bits to 0 due to the way the SHR is formed. The ATmega128RFA1 continues the reception of incoming frames as long any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the ...

Page 93

... AES_STATUS AES status register AES_CTRL AES control register AES_KEY Access to 16 Byte key buffer AES_STATE Access to 16 Byte data buffer The use of the security module requires a configuration of the security engine before starting a security operation. The following steps are required: ATmega128RFA1 37). 93 ...

Page 94

... ATmega128RFA1 94 Table 9-25. AES Engine Configuration Steps Step Description 1 Key Setup 2 AES configuration 3 Write Data 4 Start operation 5 Wait for AES finished: 1. AES_READY IRQ or 2. polling AES_DONE bit (register AES_STATUS wait for 24 µs 6 Read Data Before starting any security operation a 16 Byte key must be written to the security engine (refer to section " ...

Page 95

... The ECB encryption operation is illustrated in 96 shows the ECB decryption mode which is supported in a similar way. Figure 9-35. ECB Mode - Encryption Plaintext Encryption Block Cipher Key Encryption Ciphertext ATmega128RFA1 170 completed AES Encryption/ Decryption Figure 9-35 below. Figure 9-36 on Plaintext Encryption Block Cipher Key ...

Page 96

... Cipher Block Chaining (CBC) ATmega128RFA1 96 Figure 9-36. ECB Mode - Decryption Decryption Key Due to the nature of AES algorithm the initial key to be used when decrypting is not the same as the one used for encryption. Instead it is the last round key. This last round key is the content of the key address space stored after running one full encryption cycle and must be saved for decryption ...

Page 97

... Note that in CW mode it is not possible to transmit a RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see section "Introduction – IEEE 802.15.4-2006 Frame Format" on page recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data ATmega128RFA1 511). Figure 9- "Digital Interface 62 ...

Page 98

... Configuration ATmega128RFA1 98 for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated continuously. All register configurations shall be setup as follows before enabling Continuous Transmission Test Mode: • TX channel setting (optional); ...

Page 99

... Band pass filter CBC - Cipher block chaining CRC - Cyclic redundancy check CCA - Clear channel assessment CSMA-CA - Carrier sense multiple access/Collision avoidance ATmega128RFA1 R/ Value Description W W 0x02 Initiate Transmission, enter BUSY_TX state Perform measurement W 0x00 Disable Continuous Transmission Test Mode Reset the transceiver below ...

Page 100

... ATmega128RFA1 100 CW - Continuous wave DVREG - Voltage regulator for digital building blocks ECB - Electronic code book ED - Energy detection ESD - Electro static discharge EVM - Error vector magnitude FCF - Frame control field FCS - Frame check sequence FIFO - First in first out FTN - Filter tuning network ...

Page 101

... Charged Device Model (CDM). [5] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 [6] AT86RF231 Software Programming Model Bit ($13C) AES_REQUEST Res AES_MODE Read/Write RW R Initial Value 0 0 ATmega128RFA1 Res AES_DIR AES_IM Res1 ...

Page 102

... AES_STATUS – AES Status Register ATmega128RFA1 102 This register controls the operation of the security module. Do not access this register during AES operation to read the AES core status. A read or write access to the register stops the ongoing processing. To read the AES status use bit AES_DONE of register AES_STATUS ...

Page 103

... AES run even if it cannot be read from AES_KEY register. Note that the AES_KEY register is cleared when entering the radio transceiver SLEEP state. • Bit 7:0 – AES_KEY7:0 - AES Encryption/Decryption Key Buffer These bits represent the data buffer for the AES Encryption/Decryption key. ATmega128RFA1 ...

Page 104

... TRX_STATUS – Transceiver Status Register ATmega128RFA1 104 Bit 7 NA ($141) CCA_DONE CCA_STATUS Read/Write R Initial Value 0 Bit 3 NA ($141) TRX_STATUS3 TRX_STATUS2 Read/Write R Initial Value 0 This read-only register signals the present state of the radio transceiver as well as the status of the CCA operation. A state change is initiated by writing a state transition command to the TRX_CMD bits of register TRX_STATE ...

Page 105

... ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted acknowledgment operation must be enabled with the SLOTTED_OPERATION bit of register XAH_CTRL_0. The application software must set the SLPTR bit of register TRXPWR at the next back-off slot boundary in order to initiate a transmission of the ATmega128RFA1 Value Description 0x01 ...

Page 106

... TRX_CTRL_0 – Reserved ATmega128RFA1 106 ACK frame. For details refer to IEEE 802.15.4-2006, chapter 5.5.4.1. Values not listed in the following table are reserved. Table 9-34 TRAC_STATUS Register Bits Register Bits TRAC_STATUS2:0 • Bit 4:0 – TRX_CMD4:0 - State Control Command A write access to register bits TRX_CMD initiates a state transition of the radio transceiver towards the new state as defined by the write access ...

Page 107

... TX_AUTO_CRC_ON=1. • Bit 4:0 – Res4:0 - Reserved Bit 7 NA ($145) PA_BUF_LT1 PA_BUF_LT0 Read/Write RW RW Initial Value 1 Bit 3 NA ($145) TX_PWR3 TX_PWR2 Read/Write RW RW Initial Value 0 This register controls the output power of the transmitter. ATmega128RFA1 5 4 Res4 Res1 Res0 PA_LT1 PA_LT0 ...

Page 108

... ATmega128RFA1 108 • Bit 7:6 – PA_BUF_LT1:0 - Power Amplifier Buffer Lead Time These register bits control the enable lead time of the internal PA buffer relative to the enable time of the internal PA. This time is further used to derive a control signal for an external RF front-end to switch between receive and transmit. ...

Page 109

... A RSSI value of 0 indicates a RF input power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or equal to -10 dBm. Table 9-40 RSSI Register Bits Register Bits RSSI4:0 ATmega128RFA1 RND_VALUE0 RSSI4 R ...

Page 110

... PHY_ED_LEVEL – Transceiver Energy Detection Level Register 9.12.12 PHY_CC_CCA – Transceiver Clear Channel Assessment (CCA) Control Register ATmega128RFA1 110 Bit 7 NA ($147) ED_LEVEL7 ED_LEVEL6 Read/Write R Initial Value 1 Bit 3 NA ($147) ED_LEVEL3 ED_LEVEL2 Read/Write R Initial Value 1 This register contains the result of an Energy Detection measurement. ...

Page 111

... IEEE 802.15.4. Table 9-43 CHANNEL Register Bits Register Bits CHANNEL4:0 Bit 7 NA ($149) CCA_CS_THRES3 Read/Write RW Initial Value 1 ATmega128RFA1 Value Description 0 Mode 3a, Carrier sense OR energy above threshold 1 Mode 1, Energy above threshold 2 Mode 2, Carrier sense only 3 Mode 3b, Carrier sense AND energy above threshold ...

Page 112

... RX_CTRL – Transceiver Receive Control Register ATmega128RFA1 112 Bit 5 NA ($149) CCA_CS_THRES1 Read/Write RW Initial Value 0 Bit 3 NA ($149) CCA_ED_THRES3 Read/Write RW Initial Value 0 Bit 1 NA ($149) CCA_ED_THRES1 Read/Write RW Initial Value 1 This register sets the threshold level for the Energy Detection (ED) of the Clear Channel Assessment (CCA). • ...

Page 113

... A write access to these register bits sets the OQPSK PSDU data rate used by the radio transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. All other values are used in High Data Rate Modes. ATmega128RFA1 Value Description Antenna Diversity operation ...

Page 114

... ANT_DIV – Antenna Diversity Control Register ATmega128RFA1 114 Table 9-46 OQPSK_DATA_RATE Register Bits Register Bits OQPSK_DATA_RATE1:0 Bit 7 NA ($14D) ANT_SEL Res2 Read/Write R Initial Value 0 Bit 3 NA ($14D) ANT_DIV_EN ANT_EXT_SW_EN Read/Write RW RW Initial Value 0 This register controls the Antenna Diversity. • Bit 7 – ANT_SEL - Antenna Diversity Antenna Status This register bit signals the currently selected antenna path ...

Page 115

... Bit 7 – AWAKE_EN - Awake Interrupt Enable • Bit 6 – TX_END_EN - TX_END Interrupt Enable • Bit 5 – AMI_EN - Address Match Interrupt Enable • Bit 4 – CCA_ED_DONE_EN - End of ED Measurement Interrupt Enable • Bit 3 – RX_END_EN - RX_END Interrupt Enable ATmega128RFA1 Value Description 0 Antenna Diversity RF switch control disabled ...

Page 116

... IRQ_STATUS – Transceiver Interrupt Status Register 9.12.20 VREG_CTRL – Voltage Regulator Control and Status Register ATmega128RFA1 116 • Bit 2 – RX_START_EN - RX_START Interrupt Enable • Bit 1 – PLL_UNLOCK_EN - PLL Unlock Interrupt Enable • Bit 0 – PLL_LOCK_EN - PLL Lock Interrupt Enable ...

Page 117

... The bit is set to logic high if DVREG_EXT = 1. Table 9-54 DVDD_OK Register Bits Register Bits DVDD_OK • Bit 1:0 – DVREG_TRIM1:0 - Reserved Table 9-55 DVREG_TRIM Register Bits Register Bits DVREG_TRIM1:0 ATmega128RFA1 Value Description 0 Internal AVDD voltage regulator for the analog section is enabled. 1 Internal AVDD voltage regulator is disabled; ...

Page 118

... BATMON – Battery Monitor Control and Status Register ATmega128RFA1 118 Bit 7 NA ($151) BAT_LOW BAT_LOW_EN Read/Write RW RW Initial Value 0 Bit 3 NA ($151) BATMON_VTH3 BATMON_VTH2 Read/Write RW RW Initial Value 0 This register configures the battery monitor to observe the supply voltage at EVDD. The status of the EVDD supply voltage is accessible by reading bit BATMON_OK with respect to the actual BATMON settings ...

Page 119

... These register bits control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 4 selectable with a resolution of 0.3 pF. Table 9-60 XTAL_TRIM Register Bits Register Bits XTAL_TRIM3:0 ATmega128RFA1 Value Description 0x4 2.850V / 1.90V (BATMON_HR=1/0) 0x5 2.925V / 1.95V (BATMON_HR=1/0) 0x6 3 ...

Page 120

... RX_SYN – Transceiver Receiver Sensitivity Control Register ATmega128RFA1 120 Register Bits Bit 7 NA ($155) RX_PDT_DIS Read/Write RW Initial Value 0 Bit 5 NA ($155) Res1 Read/Write R Initial Value 0 Bit 3 NA ($155) RX_PDT_LEVEL3 Read/Write RW Initial Value 0 Bit 1 NA ($155) RX_PDT_LEVEL1 Read/Write RW Initial Value 0 This register controls the sensitivity threshold of the receiver. ...

Page 121

... MAC command frame. This may be applied to proprietary networks or networks using the High Data Rate Modes to increase battery lifetime and to improve the overall data throughput. This setting affects also to acknowledgment frame response time for slotted acknowledgment operation. ATmega128RFA1 Value Description RSSI > -51 dBm 0xF RX_THRES > ...

Page 122

... FTN_CTRL – Transceiver Filter Tuning Control Register 9.12.26 PLL_CF – Transceiver Center Frequency Calibration Control Register ATmega128RFA1 122 Table 9-62 AACK_ACK_TIME Register Bits Register Bits AACK_ACK_TIME • Bit 1 – AACK_PROM_MODE - Enable Promiscuous Mode This register bit enables the promiscuous mode within the RX_AACK mode; refer to IEEE 802 ...

Page 123

... Bit 6:0 – Resx6:0 - Reserved Bit ($15C) Read/Write Initial Value This register contains the part number of the device. • Bit 7:0 – PART_NUM7:0 - Part Number These bits decode the part number of the device according to the following table. ATmega128RFA1 2 Resx2 Resx0 Resx5 Resx4 ...

Page 124

... Bit 7:0 – MAN_ID_07:00 - Manufacturer ID (Low Byte) These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID. Table 9-65 MAN_ID_0 Register Bits Register Bits MAN_ID_07:00 Bit ($15F) Read/Write Initial Value Value Description 0x83 ATmega128RFA1 part number Value Description 2 Revision AB 3 Revision C ...

Page 125

... These bits contain the bits [15:8] of the MAC short address. Bit ($162) Read/Write Initial Value This register contains the lower 8 bits of the MAC PAN ID for Frame Filter address recognition. • Bit 7:0 – PAN_ID_07:00 - MAC Personal Area Network ID ATmega128RFA1 Value Description 0x00 Atmel JEDEC manufacturer ID, bits [15: bit manufacturer ID ...

Page 126

... PAN_ID_1 – Transceiver Personal Area Network ID Register (High Byte) 9.12.36 IEEE_ADDR_0 – Transceiver MAC IEEE Address Register 0 9.12.37 IEEE_ADDR_1 – Transceiver MAC IEEE Address Register 1 9.12.38 IEEE_ADDR_2 – Transceiver MAC IEEE Address Register 2 ATmega128RFA1 126 These bits contain the bits [7:0] of the MAC PAN ID. Bit ...

Page 127

... NA ($169) Read/Write Initial Value This register contains the bits [47:40] of the MAC IEEE address for Frame Filter address recognition. • Bit 7:0 – IEEE_ADDR_57:50 - MAC IEEE Address These bits map to the bits [47:40] of the 64 bit MAC IEEE address. ATmega128RFA1 IEEE_ADDR_37: ...

Page 128

... IEEE_ADDR_6 – Transceiver MAC IEEE Address Register 6 9.12.43 IEEE_ADDR_7 – Transceiver MAC IEEE Address Register 7 9.12.44 XAH_CTRL_0 – Transceiver Extended Operating Mode Control Register ATmega128RFA1 128 Bit ($16A) Read/Write Initial Value This register contains the bits [55:48] of the MAC IEEE address for Frame Filter address recognition. • ...

Page 129

... SLPTR of register TRXPR. This waiting state is signaled in sub register TRAC_STATUS of register TRX_STATE with value SUCCESS_WAIT_FOR_ACK. Table 9-69 SLOTTED_OPERATION Register Bits Register Bits SLOTTED_OPERATION ATmega128RFA1 Value Description 0x0 Retransmission of frame is not attempted. 0x1 Retransmission of frame is attempted once ...

Page 130

... CSMA_SEED_0 – Transceiver CSMA-CA Random Number Generator Seed Register 9.12.46 CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2 ATmega128RFA1 130 Bit ($16D) CSMA_SEED_07:00 Read/Write Initial Value This register contains the lower 8 bits of the CSMA_SEED. The upper 3 bits are part of register CSMA_SEED_1. CSMA_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm ...

Page 131

... Bit 7:4 – MAX_BE3:0 - Maximum Back-off Exponent These register bits define the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are ATmega128RFA1 Value Description 0 ...

Page 132

... TST_CTRL_DIGI – Transceiver Digital Test Control Register ATmega128RFA1 132 Table 9-71 MAX_BE Register Bits Register Bits MAX_BE3:0 • Bit 3:0 – MIN_BE3:0 - Minimum Back-off Exponent These register bits define the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for back off the CCA. For details refer to IEEE 802 ...

Page 133

... Bit 7:0 – TRXFBST7:0 - Frame Buffer Start Byte Bit ($1FF) Read/Write Initial Value This register is the last byte of the 128 byte long frame buffer of the radio transceiver. • Bit 7:0 – TRXFBEND7:0 - Frame Buffer End Byte ATmega128RFA1 Value Description 0 NORMAL (no test is active) 15 TST_CONT_TX (continuous transmit RX_LENGTH5 RX_LENGTH4 ...

Page 134

... Main Features 10.2 Clock source selection and Sleep/Active mode operation 10.3 32 bit Register Access (Atomic Read/Write) ATmega128RFA1 134 The MAC symbol counter provides symbol timing information for IEEE 802.15.4 wireless networks. The counter time base can be derived from the 16 MHz crystal or the RTC (32 ...

Page 135

... Transceiver Personal Area Network ID Register (Low Beacon timestamps can also be generated manually. Writing “1” to SCMBTS of Register SCCR0 captures the current symbol counter value and stores it in the beacon timestamp register. The bit is cleared automatically afterwards. ATmega128RFA1 "Interrupt Vectors in ATmega128RFA1" "PAN_ID_0 – Byte)" on page 125. ...

Page 136

... Interrupt Control Registers 10.9 Backoff Slot Counter 10.10 Symbol Counter Usage 10.10.1 SFD and Beacon Timestamp Generation ATmega128RFA1 136 It is also possible to manually set the register in order to provide a distinct starting value for the relative compare modes (see next section). The compare unit contains 3 independent 32 bit compare modules and is used to compare the current counter value with the value stored in the compare register, and optionally the beacon timestamp register ...

Page 137

... A typical superframe timing scenario using the symbol counter relative compare mode is shown in Figure 10-2 on page 138. The Symbol Counter values in the figure do not reflect realistic time intervals but demonstrate the principle of operation. ATmega128RFA1 137 ...

Page 138

... Register Description 10.11.1 SCCNTHH – Symbol Counter Register HH-Byte ATmega128RFA1 138 Figure 10-2. Relative Compare Mode The compare match registers are programmed with symbol intervals relative to the beacon frame SFD timestamp. For instance the SCCMP1 is programmed to 80, because the first Granted Time Slot (GTS1) is expected 80 symbols after the beacon frame ...

Page 139

... This register contains the least significant byte of the 32 bit Symbol Counter. • Bit 7:0 – SCCNTLL7:0 - Symbol Counter Register LL-Byte Bit ($EC) Read/Write Initial Value This register contains the most significant byte of the 32 bit frame (SFD) timestamp register • Bit 7:0 – SCTSRHH7:0 - Symbol Counter Frame Timestamp Register HH-Byte ATmega128RFA1 SCCNTHL7 ...

Page 140

... SCTSRHL – Symbol Counter Frame Timestamp Register HL-Byte 10.11.7 SCTSRLH – Symbol Counter Frame Timestamp Register LH-Byte 10.11.8 SCTSRLL – Symbol Counter Frame Timestamp Register LL-Byte 10.11.9 SCBTSRHH – Symbol Counter Beacon Timestamp Register HH-Byte ATmega128RFA1 140 Bit ($EB) Read/Write Initial Value ...

Page 141

... This register contains the least significant byte of the 32 bit Beacon Timestamp Register. • Bit 7:0 – SCBTSRLL7:0 - Symbol Counter Beacon Timestamp Register LL-Byte Bit ($F8) Read/Write Initial Value This register contains the most significant byte of the 32 bit compare value for the first compare unit ATmega128RFA1 SCBTSRHL7 ...

Page 142

... SCOCR1LH – Symbol Counter Output Compare Register 1 LH-Byte 10.11.16 SCOCR1LL – Symbol Counter Output Compare Register 1 LL-Byte 10.11.17 SCOCR2HH – Symbol Counter Output Compare Register 2 HH-Byte ATmega128RFA1 142 • Bit 7:0 – SCOCR1HH7:0 - Symbol Counter Output Compare Register 1 HH-Byte Bit ...

Page 143

... Bit 7:0 – SCOCR2LL7:0 - Symbol Counter Output Compare Register 2 LL-Byte Bit ($F0) Read/Write Initial Value This register contains the most significant byte of the 32 bit compare value for the third compare unit • Bit 7:0 – SCOCR3HH7:0 - Symbol Counter Output Compare Register 3 HH-Byte ATmega128RFA1 SCOCR2HL7 ...

Page 144

... SCOCR3HL – Symbol Counter Output Compare Register 3 HL-Byte 10.11.23 SCOCR3LH – Symbol Counter Output Compare Register 3 LH-Byte 10.11.24 SCOCR3LL – Symbol Counter Output Compare Register 3 LL-Byte 10.11.25 SCCR0 – Symbol Counter Control Register 0 ATmega128RFA1 144 Bit ($EF) Read/Write Initial Value This register contains the second most significant byte of the 32 bit compare value for the third compare unit • ...

Page 145

... SCBTS+SCOCR1). Otherwise, the counter is compared against the copare register 1 (SCCNT == SCOCR1). Bit ($DD) Res6 Res5 Res4 Read/Write Initial Value ATmega128RFA1 Resx4 Resx3 Resx2 Resx1 SCENBO SCCR1 ...

Page 146

... SCSR – Symbol Counter Status Register 10.11.28 SCIRQS – Symbol Counter Interrupt Status Register ATmega128RFA1 146 This register is used to enable the backoff slot counter. • Bit 7:5 – Res6:4 - Reserved Bit This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. • ...

Page 147

... This bit enables the SCNT_CMP3 interrupt. • Bit 1 – IRQMCP2 - Symbol Counter Compare Match 2 IRQ enable This bit enables the SCNT_CMP2 interrupt. • Bit 0 – IRQMCP1 - Symbol Counter Compare Match 1 IRQ enable This bit enables the SCNT_CMP1 interrupt. ATmega128RFA1 IRQMBO IRQMOF IRQMCP3 IRQMCP2 IRQMCP1 ...

Page 148

... Oscillator (32.768kHz) 11.2 Clock Systems and their Distribution 11.2.1 CPU Clock – clk CPU ATmega128RFA1 148 This section describes the clock options for the AVR microcontroller. Figure 11-1 below presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce ...

Page 149

... SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting using any available programming interface. Any clock source needs a minimum number of oscillating cycles before it can be considered stable. ATmega128RFA1 (1) CKSEL3:0 1111 – 0110 0101 - 0100 ...

Page 150

... Calibrated Internal RC Oscillator ATmega128RFA1 150 To ensure sufficient startup time, the device issues an internal reset with a time-out delay (t ) after the device reset is released by all other reset sources. Section TOUT "Power-on Reset" on page 178 describes the start conditions for the internal reset. The ...

Page 151

... Slowly rising power drive the device from an external clock source, CLKI should be used as shown in Figure 11-2 on page 152. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. ATmega128RFA1 "Calibration Byte" on page (1)(2) CKSEL3:0 0010 Additional Delay from ...

Page 152

... Transceiver Crystal Oscillator ATmega128RFA1 152 Figure 11-2. External Clock Drive Configuration external clock CLKI VSS When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 11-8 below. Table 11-7. External Clock Frequency Nominal Frequency 0 – 16 MHz Table 11-8 ...

Page 153

... See section crystal connection. The ATmega128RFA1 has a system clock prescaler, and the system clock can be divided by setting the “CLKPR – Clock Prescale Register”. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low ...

Page 154

... Interrupts must be disabled when changing prescaler settings to make sure the write procedure is not interrupted not required to change the prescaler setting of an existing software package written for an 8MHz internal RC oscillator. The change of the prescaler (additional 1:2 divider) is compensated by doubling the RC oscillator frequency of the ATmega128RFA1. Bit 7 6 ...

Page 155

... The device is shipped with the CKDIV8 Fuse programmed. Table 11-12 CLKPS Register Bits Register Bits CLKPS3:0 ATmega128RFA1 Value Description 0xff Calibration value for highest oscillator frequency ...

Page 156

... ATmega128RFA1 156 Register Bits Value Description 0xB Reserved 0xC Reserved 0xD Reserved 0xE Reserved 0xF Division factor 1 only permitted for RC- Oscillator. Flash and EEPROM programming is not allowed. 8266B-MCU Wireless-03/11 ...

Page 157

... Deep-sleep mode to avoid an undefined ADC operation. In chapter "System Clock and Clock Options" on page 148 in the ATmega128RFA1, and their distribution were presented. 148 is helpful in selecting an appropriate sleep mode. The following table shows the different sleep modes and their wake-up sources. ...

Page 158

... Active Clock Domains Power-down Power-save (1) Standby Extended Standby 12.2.1 Idle Mode 12.2.2 ADC Noise Reduction Mode ATmega128RFA1 158 Oscillators (3) X ( (2) (2) ( Notes: 1. Only recommended with external crystal or resonator selected as clock source Timer/Counter2 is running in asynchronous mode. 3. For INT7:4, only level interrupt. To enter any of the sleep modes, the SE bit in in the SMCR register (see Sleep Mode Control Register" ...

Page 159

... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. ATmega128RFA1 for details. "System Clock "8-bit 310 ...

Page 160

... Power Reduction Register 12.4 Minimizing Power Consumption 12.4.1 Analog to Digital Converter 12.4.2 Analog Comparator 12.4.3 Brown-out Detector 12.4.4 Internal Voltage Reference ATmega128RFA1 160 The Power Reduction Register (PRR), see page 168, "PRR1 – Power Reduction Register 1" on page 169 Reduction Register 2" on page peripherals to reduce power consumption ...

Page 161

... Power Reduction Register 1" on page 169 The radio transceiver is derived from a stand alone solution that was partly controlled by external pins. Now the radio transceiver is fully controlled by individual register bits. ATmega128RFA1 "Watchdog Timer" on page 181 ) and the ADC clock (clk ...

Page 162

... Supply Voltage and Leakage Control 12.5.1 Power-chain Figure 12-1. Power-chain connections ATmega128RFA1 162 The radio transceiver has a separate reset signal. A radio transceiver reset is initiated by setting bit TRXRST in register TRXPR. This bit is self-resetting. The radio transceiver signal SLPTR can be controlled by the bit SLPTR in register TRXPR and is used to set the radio transceiver into SLEEP mode (assuming TRX_STATE is TRX_OFF) ...

Page 163

... The SRAM blocks may be configured separately to decrease their leakage current (see section "SRAM with Data Retention" on The following table shows the different implemented sleep modes and the behavior of the power-chain depending on the current state of the radio transceiver. ATmega128RFA1 + ·t DRT_ON PWRSW_ON ...

Page 164

... SRAM with Data Retention ATmega128RFA1 164 Table 12-2. Power states of microcontroller and radio transceiver AVR State Radio Transceiver State off (SLEEP or power reduction) (1…6) off ON (1,4…6) off off (SLEEP or power reduction) (2,3) off off (SLEEP or power reduction) DEEP SLEEP Notes: 1 ...

Page 165

... Reading value 0 indicates that the internal supply voltage is disabled or not yet settled to the final value. In case the the ATmega128RFA1 is not supplied with a sufficient (D)EVDD and the digital voltage regulator output voltage is too low, a power on reset (POR) is initiated. ...

Page 166

... Low Leakage Voltage Regulator (LLVREG) 12.5.5 Low Leakage Voltage Regulator Control ATmega128RFA1 166 The main digital voltage regulator (DVREG) will be switched off during the DEEP_SLEEP modes “power-down” and “power-save”. The Low Leakage Voltage Regulator will then keep the digital supply voltage to provide data retention. No application software control is required ...

Page 167

... IOST LLDRL,r19 ; write LLDRL second IOST LLCR,r20 ; bit 0 cleared = disable automatic calibration ; poll LLCAL bit of LLCR to check if automatic calibration is ; turned of wait_calib: IOLD r20,LLCR sbrc r20,3 rjmp wait_calib ; not executed if bit 3 of LLCR is cleared … ATmega128RFA1 th power-up time and use the 167 ...

Page 168

... Register Description 12.6.1 SMCR – Sleep Mode Control Register 12.6.2 PRR0 – Power Reduction Register0 ATmega128RFA1 168 Bit $33 ($53) Res3 Res2 Res1 Read/Write Initial Value The Sleep Mode Control Register contains control bits for power management. • Bit 7:4 – Res3:0 - Reserved • ...

Page 169

... Writing a logic one to this bit shuts down the Timer/Counter5 module. When the Timer/Counter5 is enabled, operation will continue like before the shutdown. • Bit 4 – PRTIM4 - Power Reduction Timer/Counter4 Writing a logic one to this bit shuts down the Timer/Counter4 module. When the Timer/Counter4 is enabled, operation will continue like before the shutdown. ATmega128RFA1 ...

Page 170

... PRR2 – Power Reduction Register 2 12.6.5 TRXPR – Transceiver Pin Register ATmega128RFA1 170 • Bit 3 – PRTIM3 - Power Reduction Timer/Counter3 Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown. ...

Page 171

... During "Deep-Sleep" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used. Otherwise the SRAM is switched off (disconnected from the power supply) and all its data are lost. • Bit 3:0 – Resx3:0 - Reserved ATmega128RFA1 ...

Page 172

... DRTRAM1 – Data Retention Configuration Register of SRAM 1 12.6.8 DRTRAM2 – Data Retention Configuration Register of SRAM 2 ATmega128RFA1 172 Bit ($134) Res1 Res0 DRTSWOK ENDRT Read/Write Initial Value The DRTRAM1 register controls the behavior of SRAM block 1 in the power-states "power-save" and "power-down". To prevent any data loss the SRAM will not completely disconnected from the power supply ...

Page 173

... Bit 4 – LLCOMP - Comparator Output This bit indicates the output state of the comparator of the low-leakage voltage regulator. In this way the calibration progress can be directly monitored for debug purposes. The state of the bit changes at most every 64kHz clock period. ATmega128RFA1 ...

Page 174

... LLDRH – Low Leakage Voltage Regulator Data Register (High-Byte) ATmega128RFA1 174 • Bit 3 – LLCAL - Calibration Active This bit indicates that the automatic calibration is in progress. The analog part of the calibration circuit is powered up if the bit is 1. • Bit 2 – LLTCO - Temperature Coefficient of Current Source This bit shows the status of the selection of the temperature coefficient ...

Page 175

... Characteristics" for details. • Bit 7:6 – PFDRV1:0 - Driver Strength Port F Table 12-7 PFDRV Register Bits Register Bits PFDRV1:0 • Bit 5:4 – PEDRV1:0 - Driver Strength Port E Table 12-8 PEDRV Register Bits Register Bits PEDRV1:0 ATmega128RFA1 Res0 LLDRL3 LLDRL2 LLDRL1 LLDRL0 R RW ...

Page 176

... DPDS1 – Port Driver Strength Register 1 ATmega128RFA1 176 Register Bits • Bit 3:2 – PDDRV1:0 - Driver Strength Port D Table 12-9 PDDRV Register Bits Register Bits PDDRV1:0 • Bit 1:0 – PBDRV1:0 - Driver Strength Port B Table 12-10 PBDRV Register Bits Register Bits ...

Page 177

... The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in Sources" on page 149. The ATmega128RFA1 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). ...

Page 178

... Power-on Reset ATmega128RFA1 178 Figure 13-1. Reset Logic EVDD Brown-out Reset Circuit BODLEVEL [2..0] DEVDD Power-on Reset Circuit Pull-up Resistor SPIKE RSTN Reset Circuit FILTER JTAG Reset Watchdog Register Timer Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] A Power-on Reset (POR) pulse is generated by a dynamic, on-chip detection circuit. ...

Page 179

... TIME-OUT INTERNAL RESET ATmega128RFA1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the EVDD level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should ...

Page 180

... TOUT TIME-OUT INTERNAL RESET ATmega128RFA1 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. ...

Page 181

... WDE WDIF WDIE ATmega128RFA1 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR -Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...

Page 182

... ATmega128RFA1 182 program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit ...

Page 183

... Note: 1. The example code assumes that the part specific header file is included. 2. The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATmega128RFA1 183 ...

Page 184

... Register Description 13.5.1 MCUSR – MCU Status Register 13.5.2 WDTCSR – Watchdog Timer Control Register ATmega128RFA1 184 Bit $34 ($54) Res2 Res1 Res0 Read/Write Initial Value The MCU Status Register provides information on which reset source caused an MCU reset. To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program ...

Page 185

... Bit 5, 2:0 – WDP3:0 – Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. Table 13-2. WDP Register Bits Register Bits WDP3:0 ATmega128RFA1 Mode Action on Time-out Stopped None Interrupt Mode Interrupt ...

Page 186

... ATmega128RFA1 186 Register Bits Value Description 0x04 Oscillator Cycles 32k, (0.25s) 0x05 Oscillator Cycles 64k, (0.5s) 0x06 Oscillator Cycles 128k, (1.0s) 0x07 Oscillator Cycles 256k, (2.0s) 0x08 Oscillator Cycles 512k, (4.0s) 0x09 Oscillator Cycles 1024k, (8.0s) 8266B-MCU Wireless-03/11 ...

Page 187

... I/O-Ports 14.1 Introduction 8266B-MCU Wireless-03/11 All ATmega128RFA1 ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions ...

Page 188

... Ports as General Digital I/O 14.2.1 Configuring the Port 14.2.2 Configuring the Pin ATmega128RFA1 188 The ports are bi-directional I/O ports with optional internal pull-ups. shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 14-2. General Digital I/O DPDS0/DPDS1 ...

Page 189

... This is needed to avoid meta-stability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 14-3 on synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t ATmega128RFA1 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext ...

Page 190

... ATmega128RFA1 190 Figure 14-3. Synchronization when reading an external applied pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low ...

Page 191

... Sleep mode, as the clamping in these sleep mode produces the requested logic change. If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as ATmega128RFA1 "Alternate Port 191 ...

Page 192

... Alternate Port Functions ATmega128RFA1 192 described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset-, Active- and Idle-mode). The simplest method to ensure a defined level of an unused pin is to enable the internal pull-up ...

Page 193

... Refer to the alternate function description for further details. The Port B pins with alternate functions are shown in the following table. ATmega128RFA1 Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010 ...

Page 194

... ATmega128RFA1 194 Table 14-3. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0, Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7) PB6 OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt 6) ...

Page 195

... Table 14-4. Overriding Signals for Alternate Functions in PB7:PB4 Signal PB7/OC0A/OC1C PB6/OC1B Name PUOE 0 0 ATmega128RFA1 "Serial Downloading" on page 478 "Serial Downloading" on page 478 page 196 relate the alternate functions of Port B to page 192. SPI MSTR INPUT and SPI PB5/OC1A PB4/OC2A 0 0 for for details) ...

Page 196

... Alternate Functions of Port D ATmega128RFA1 196 Signal PB7/OC0A/OC1C PB6/OC1B Name PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE OC0/OC1C OC1B ENABLE ENABLE PVOV OC0/OC1C OC1B DIEOE PCINT7•PCIE0 PCINT6•PCIE0 DIEOV PCINT7 INPUT PCINT6 INPUT AIO – – Table 14-5. Overriding Signals for Alternate Functions in PB3:PB0 ...

Page 197

... Table 14-7. Overriding Signals for Alternate Functions PD7:PD4 Signal PD7/T0 PD6/T1 Name PUOE 0 0 PUOV 0 0 DDOE 0 0 ATmega128RFA1 page 198 relates the alternate functions of Port D Figure 14-5 on page 192. PD5/XCK1 0 0 XCK1 OUTPUT ENABLE PD4/ICP1 197 ...

Page 198

... Alternate Functions of Port E ATmega128RFA1 198 Signal PD7/T0 PD6/T1 Name DDOV 0 0 PVOE 0 0 PVOV 0 0 DIEOE 0 0 DIEOV INPUT T1 INPUT AIO – – Table 14-8. Overriding Signals for Alternate Functions PD3:PD0 Signal PD3/INT3/TXD1 PD2/INT2/RXD1 Name PUOE TXEN1 RXEN1 PUOV 0 PORTD2&(~PUD) ...

Page 199

... XCK0, this is the USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. • TXD0 – Port E, Bit 1 TXD0, this is the USART0 Transmit pin. • RXD0/PCINT8 – Port E, Bit 0 ATmega128RFA1 199 ...

Page 200

... Alternate Functions of Port F ATmega128RFA1 200 RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin input, a logical one in PORTE0 will turn on the internal pull-up ...

Related keywords