ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 163

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12-2. Timing visualization of power up
Figure 12-3. Timing visualization of wakeup from DEEP_SLEEP
8266B-MCU Wireless-03/11
R S T O N
S L E E P
P O R
t
P O R
b a n d g a p
b a n d g a p
s t a r t u p
s t a r t u p
t
t
B G
B G
D V R E G
D V R E G
s t a r t u p
t
s t a r t u p
t
D V R E G
D V R E G
3. first SRAM block (lower 4k bytes),
4. last SRAM block (upper 4k bytes),
5. Radio transceiver including AES engine,
6. Non-volatile memory.
If the power-chain is completely enabled the standard AVR wake-up procedure
continues.
Figure 12-2 shows the chained startup procedure after power up. The Figure 12-3
shows the startup from DEEP_SLEEP. A module is only switched on if it is not
deselected by power reduction register (PRR1 or PRR2). This is possible for SRAM
blocks and radio transceiver power switch. At the end of the startup, the pin RSTON is
enabled. Depending of the currently enabled memory blocks (N
procedure takes different time.
t
The SRAM is organized in 4kByte blocks, the NVM in 128kByte blocks. Deselected
SRAM blocks (by PRR2 register) reduce the wakeup time from DEEP_SLEEP. For
further timing information see
506.
Sleep
Six sleep modes are defined for the CPU. Disabling the power-chain and thus switching
off of the above mentioned blocks makes only sense for the modes “power-down” and
“power-save”. Also an enabled radio transceiver prevents the power-chain from being
disabled.
In order to disable the power-chain, one of the following conditions must fit:
• The radio transceiver has to be disabled (power reduction register PRR1 bit
• The radio transceiver is sent into SLEEP mode (register TRXPR bit SLPTR).
The SRAM blocks may be configured separately to decrease their leakage current (see
section
The following table shows the different implemented sleep modes and the behavior of
the power-chain depending on the current state of the radio transceiver.
STARTUP_TOTAL
D R T s w i t c h
D R T s w it c h
S R A M # 0
t
PRTRX24).
S R A M # 0
t
D R T _ O N
D R T _ O N
"SRAM with Data Retention" on
D R T s w it c h
= t
D R T s w i t c h
S R A M # 1
t
S R A M # 1
t
D R T _ O N
D R T _ O N
BG
+ t
DVREG
D R T s w i t c h
D R T s w i t c h
S R A M # 2
t
S R A M # 2
t
D R T _ O N
D R T _ O N
+ N
t
"Power Management Electrical Characteristics" on page
t
SRAM
S T A R T U P
S T A R T U P
·t
D R T s w it c h
DRT_ON
D R T s w i t c h
S R A M # 3
t
S R A M # 3
t
D R T _ O N
D R T _ O N
page 164).
+ 3 t
p o w e r s w i t c h
p o w e r s w it c h
t
PWRSW_ON
r a d i o t r a n s .
t
r a d i o t r a n s .
P W R S W _ O N
P W R S W _ O N
ATmega128RFA1
+ t
p o w e r s w i t c h
t
p o w e r s w i t c h
t
P W R S W _ O N
P W R S W _ O N
OSC_STARTUP
N V M
N V M
SRAM
t
t
O S C _ S T A R T U P
O S C _ S T A R T U P
o s c il l a t o r
o s c il l a t o r
s t a r t u p
s t a r t u p
), the startup
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