ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 323

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.10 Timer/Counter Prescaler
8266B-MCU Wireless-03/11
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
• During asynchronous operation, the synchronization of the Interrupt Flags for the
• If the CPU wakes up from asynchronous timer and goes back to sleep again, it may
Figure 21-12. Prescaler for Timer/Counter2
The register ASSR defines the clock source for the asynchronous Timer/Counter2. The
clock source for Timer/Counter2 is named clk
main system I/O clock clk
asynchronously clocked either from the TOSC1 or from the AMR pin. This enables the
use of Timer/Counter2 as a Real Time Counter (RTC).
EXCLKAMR
PS RASY
advanced by at least one before the processor can read the counter value. After
wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading
TCNT2 must be done through a register synchronized to the internal I/O clock
domain. Synchronization takes place for every rising TOSC1 edge. When waking up
from Powersave mode, and the I/O clock (clk
read as the previous value (before entering sleep) until the next rising TOSC1 edge.
The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for
reading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2x or TCCR2x.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is
therefore advanced by at least one before the processor can read the timer value
causing the setting of the Interrupt Flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
wakeup multiple times or the IRQ is called multiple times. This may be avoided if the
CPU waits with the next sleep instruction until the next asynchronous clock arrives.
TOSC1
CS20
CS21
CS22
clk
AMR
AS2
I/O
IO
clk
. By setting the AS2 bit in ASSR, Timer/Counter2 is
T2S
Clear
TIMER/ COUNTER2 CLOCK SOURCE
T2S
0
I/O
. clk
) again becomes active, TCNT2 will
10-BI T T/C PRES CA LER
ATmega128RFA1
T2S
clk
is by default connected to the
T2
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