ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 436

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28 JTAG Interface and On-chip Debug System
28.1 Features
28.2 Overview
436
ATmega128RFA1
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG)
• Debugger Access to:
• Extensive on-chip debug Support for Break Conditions, Including
• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
• On-chip debugging Supported by AVR Studio
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-scan capability
• Programming the non-volatile memories, Fuses and Lock bits
• On-chip debugging
A brief description is given in the following sections. Detailed descriptions for
Programming via the JTAG interface, and using the Boundary-scan Chain can be found
in the sections
via the JTAG Interface" on page
considered being private JTAG instructions, and distributed within ATMEL and to
selected third party vendors only.
Figure 28-1 on
debug system. The TAP Controller is a state machine controlled by the TCK and TMS
signals. The TAP Controller selects either the JTAG Instruction Register or one of
several Data Registers as the scan chain (Shift Register) between the TDI – input and
TDO – output. The Instruction Register holds JTAG instructions controlling the behavior
of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data
Registers used for board-level testing. The JTAG Programming Interface (actually
consisting of several physical and virtual Data Registers) is used for serial programming
via the JTAG interface. The internal scan-chain and breakpoint scan-chain are used for
on-chip debugging only.
Standard
Interface
o All Internal Peripheral Units
o Internal and External RAM
o The Internal Register File–Program Counter
o EEPROM and Flash Memories
o AVR Break Instruction
o Break on Change of Program Memory Flow
o Single Step Break
o Program Memory Breakpoints on Single Address or Address Range
o Data Memory Breakpoints on Single Address or Address Range
"Programming via the JTAG Interface" on page 482
page 437 shows a block diagram of the JTAG interface and the on-chip
482, respectively. The on-chip debug support is
®
8266B-MCU Wireless-03/11
and
"Programming