ATMEGA128RFA1-ZU Atmel, ATMEGA128RFA1-ZU Datasheet - Page 333

• Manufacturer Part Number: ATMEGA128RFA1-ZU
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Rf Ic Case Style: QFN
• No. Of Pins: 64
• Supply Voltage Range: 1.8V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8266B-MCU Wireless-03/11
control logic will sample the incoming signal of the SCK pin. To ensure correct sampling
of the clock signal, the minimum low and high periods should be:
Low period:
High period:
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS
overridden according to Table 21-1. For more details on automatic port overrides, refer
to
Table 22-1. Pin Overrides
Note:
The following code examples show how to initialize the SPI as a Master and how to
perform a simple transmission. DDR_SPI in the examples must be replaced by the
actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and
DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI
is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
Assembly Code Example
"Alternate Port Functions" on page
SPI_MasterInit:
SPI_MasterTransmit:
Wait_Transmit:
MOSI
MISO
SCK
Pin
SS
; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ret
; Start transmission of data (r16)
out SPDR,r16
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
1.
See
to define the direction of the user defined SPI pins.
Direction, Master SPI
User Defined
Input
User Defined
User Defined
longer than 2 CPU clock cycles
longer than 2 CPU clock cycles
"Alternate Functions of Port B" on page 193
(1)
(1)
192.
ATmega128RFA1
Direction, Slave SPI
Input
User Defined
Input
Input
for a detailed description of how
__
pins is
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